key_display.v

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· Verilog 代码 · 共 23 行

`timescale 1ns / 1ps

module key_display(clk, rst, button, seven, an,bn2,bn3);
    input clk;
    input rst;
    input [3:0] button;
    
    output [6:0] seven;
    output [3:0] an;
	 output [3:0] bn2;
	 output [3:0] bn3;
    wire clkout;
    wire [3:0] bn0;
	 wire [3:0] bn1;
	 wire [3:0] bn2;
	 wire [3:0] bn3;

clkdiv m1(.clk(clk),.rst(rst),.clkout(clkout));
buttonte m2(.clkout(clkout),.rst(rst),.button(button),.bn0(bn0),.bn1(bn1),.bn2(bn2),.bn3(bn3));
change m3(.clkout(clkout),.rst(rst),.bn0(bn0),.bn1(bn1),.bn2(bn2),.bn3(bn3),.seven(seven),.an(an));

endmodule