vga_key.edn

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· EDN 代码 · 共 1,386 行 · 第 1/5 页

(edif vga_key
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2008 5 3 16 18 17)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "8.1.0, Build 540R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
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       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
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    (cell LUT4_L (cellType GENERIC)
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         (interface
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           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT4 (cellType GENERIC)
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         (interface
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    (cell LUT3_L (cellType GENERIC)
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    (cell LUT2_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
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    (cell LUT1_L (cellType GENERIC)
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    (cell MULT_AND (cellType GENERIC)
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    (cell MUXCY (cellType GENERIC)
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       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
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  )
  (library UNILIB
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           (port C (direction INPUT)
 )
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    (cell FDE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
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           (port CE (direction INPUT))
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           (port Q (direction OUTPUT))
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           (port CLR (direction INPUT))
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    (cell INV (cellType GENERIC)
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         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
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    )
    (cell GND (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port G (direction OUTPUT))
         )
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    )
    (cell VCC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port P (direction OUTPUT))
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  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell change (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename bn1 "bn1[3:0]") 4) (direction INPUT))
           (port (array (rename bn0 "bn0[3:0]") 4) (direction INPUT))
           (port (array (rename bn3 "bn3[3:0]") 4) (direction INPUT))
           (port (array (rename bn2 "bn2[3:0]") 4) (direction INPUT))
           (port (array (rename ea_c "ea_c[3:0]") 4) (direction OUTPUT))
           (port (array (rename seven_c "seven_c[6:0]") 7) (direction OUTPUT))
           (port rst_c_i (direction INPUT))
           (port clkout (direction INPUT))
         )
         (contents
          (instance (rename seven_0 "seven[0]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename seven_1 "seven[1]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename seven_2 "seven[2]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename seven_3 "seven[3]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename seven_4 "seven[4]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename seven_5 "seven[5]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename seven_6 "seven[6]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename an_0 "an[0]") (viewRef PRIM (cellRef FDP (libraryRef UNILIB)))
          )
          (instance (rename an_1 "an[1]") (viewRef PRIM (cellRef FDP (libraryRef UNILIB)))
          )
          (instance (rename an_2 "an[2]") (viewRef PRIM (cellRef FDP (libraryRef UNILIB)))
          )