vga.v

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· Verilog 代码 · 共 39 行

`timescale 1ns / 1ps

module vga(clk, rst,sw2,but3,but4,hs, vs, red, green, blue);
    input clk;
    input rst;
	 input sw2;
	 input [3:0] but4;
	 input [3:0] but3;
  //  input [63:0] date_in;
    output hs;
    output vs;
    output [2:0] red;
    output [2:0] green;
    output [1:0] blue;
	// output [14:0] addrb;
	 wire   [9:0] counths;
	 wire   [9:0] countvs;
	 wire hs;
	 wire vs;
	 wire [14:0] addra;
	 wire [14:0] addrb;
	 wire web;
	 wire wea;
	 wire dina;
	 wire doutb;
	// wire ena;
    wire ssra;
	 //wire [14:0] addre2;
	


vs_hs m1 (.clk(clk),.hs(hs),.vs(vs),.rst(rst),.counths(counths),.countvs(countvs));
savecon m2(.clk(clk),.rst(rst),.date(doutb),.but3(but3),.but4(but4),.counths(counths),.countvs(countvs),.red(red),.green(green),.blue(blue),.addre2(addrb),.web(web));
save m3(.clka(clk),.clkb(clk),.dina(dina),.ssra(ssra),.doutb(doutb),.addra(addra),.addrb(addrb),.wea(wea),.web(web));
sendsave m4(.clk(clk),.rst(rst),.ssra(ssra),.sw2(sw2),.addr(addra),.din(dina),.wea(wea));
//savecon1  m2(.clk(clk),.rst(rst),.date(doutb),.but4(but4),.counths(counths),.countvs(countvs),.red(red),.green(green),.blue(blue),.addre2(addrb),.web(web));

endmodule