vga_key.par

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· PAR 代码 · 共 241 行

Release 8.2.03i par I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

QIAOYANG::  Sat May 03 16:13:12 2008

par -w -intstyle ise -ol std -t 1 vga_key_map.ncd vga_key.ncd vga_key.pcf 


Constraints file: vga_key.pcf.
Loading device for application Rf_Device from file '3s100e.nph' in environment F:\Xilinx.
   "vga_key" is an NCD, version 3.1, device xc3s100e, package tq144, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)


Device speed data version:  "PRODUCTION 1.26 2006-08-18".


Design Summary Report:

 Number of External IOBs                          28 out of 108    25%

   Number of External Input IOBs                  7

      Number of External Input IBUFs              7
        Number of LOCed External Input IBUFs      7 out of 7     100%


   Number of External Output IOBs                21

      Number of External Output IOBs             21
        Number of LOCed External Output IOBs     21 out of 21    100%


   Number of External Bidir IOBs                  0


   Number of BUFGMUXs                  2 out of 24      8%
   Number of RAMB16s                   2 out of 4      50%
   Number of Slices                  378 out of 960    39%
      Number of SLICEMs                0 out of 480     0%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 

Starting initial Timing Analysis.  REAL time: 10 secs 
Finished initial Timing Analysis.  REAL time: 10 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98a1c8) REAL time: 12 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 14 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 14 secs 

Phase 4.2
......
..............


Phase 4.2 (Checksum:989e57) REAL time: 22 secs 

Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 22 secs 

Phase 6.8
.................................
...
...................................................................
...
....
.............
Phase 6.8 (Checksum:b05341) REAL time: 29 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 29 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 38 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 38 secs 

Writing design to file vga_key.ncd


Total REAL time to Placer completion: 39 secs 
Total CPU time to Placer completion: 34 secs 

Starting Router

Phase 1: 2604 unrouted;       REAL time: 42 secs 

Phase 2: 2403 unrouted;       REAL time: 42 secs 

Phase 3: 557 unrouted;       REAL time: 43 secs 

Phase 4: 557 unrouted; (35792)      REAL time: 43 secs 

Phase 5: 812 unrouted; (7452)      REAL time: 46 secs 

Phase 6: 855 unrouted; (3654)      REAL time: 46 secs 

Phase 7: 0 unrouted; (14657)      REAL time: 56 secs 

Phase 8: 0 unrouted; (14657)      REAL time: 58 secs 

Phase 9: 0 unrouted; (14657)      REAL time: 1 mins 38 secs 

Phase 10: 0 unrouted; (12398)      REAL time: 1 mins 49 secs 

Phase 11: 0 unrouted; (10155)      REAL time: 1 mins 56 secs 

Phase 12: 0 unrouted; (10155)      REAL time: 2 mins 3 secs 

Phase 13: 0 unrouted; (10155)      REAL time: 2 mins 4 secs 


Total REAL time to Router completion: 2 mins 4 secs 
Total CPU time to Router completion: 1 mins 57 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           m2/clkout | BUFGMUX_X2Y10| No   |   47 |  0.027     |  0.067      |
+---------------------+--------------+------+------+------------+-------------+
|               clk_c |  BUFGMUX_X1Y0| No   |  129 |  0.036     |  0.073      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.840
   The MAXIMUM PIN DELAY IS:                               3.299
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.709

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1689         743         140           4           0           0

Timing Score: 10155

INFO:Par:62 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in your
   design.
   

   Review the timing report using Timing Analyzer (In ISE select "Post-Place &
      Route Static Timing Report").  Go to the failing constraint(s) and select
      the "Timing Improvement Wizard" link for suggestions to correct each problem.

   Increase the PAR Effort Level setting to "high"

   Rerun Map with "-timing" (ISE process "Perform Timing -Driven
   Packing and Placement"

   Run Multi-Pass Place and Route in PAR using at least 5 "PAR Iterations"
   (ISE process "Multi Pass Place & Route").

   Use the Xilinx "xplorer" script to try special combinations of
   options known to produce very good results.
   See http://www.xilinx.com/xplorer for details.

   Visit the Xilinx technical support web at http://support.xilinx.com and go to
   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
   in your design.

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------
* TS_clk = PERIOD TIMEGRP "clk" 9.502 ns HI | 9.502ns    | 10.387ns   | 9      | -0.885ns   | 32      
  GH 50%                                    |            |            |        |            |         
------------------------------------------------------------------------------------------------------
* TS_m2_m1_clkout_c = PERIOD TIMEGRP "m2_m1 | 4.148ns    | 4.169ns    | 2      | -0.021ns   | 1       
  _clkout_c" 4.148 ns HIGH 50%              |            |            |        |            |         
------------------------------------------------------------------------------------------------------


2 constraints not met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 mins 9 secs 
Total CPU time to PAR completion: 2 mins 1 secs 

Peak Memory Usage:  140 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - 33 errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file vga_key.ncd



PAR done!