blk_mem_gen_release_notes.txt

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COPYRIGHT (c) 2004 XILINX, INC.
ALL RIGHTS RESERVED

Core name            : Block Memory Generator 
Version              : v1.1
Release Date         : January 18, 2006
File                 : blk_mem_gen_release_notes.txt

Revision History
Date     By            Version   Change Description
========================================================================
01/2006  Xilinx, Inc.  1.0       Initial creation.
========================================================================

INTRODUCTION
RELEASE NOTES
  1. General Core Design
    1.1 Enhancements
    1.2 Resolved Issues
    1.3 Outstanding Issues
  2. General Simulation
  3. Documentation
OTHER GENERAL INFORMATION
TECHNICAL SUPPORT

========================================================================

INTRODUCTION
============
Thank you using the Block Memory Generator (Blk Mem Gen) core from
Xilinx!  In order to obtain the latest core updates and documentation, 
please visit the Intellectual Property page located at:
http://www.xilinx.com/ipcenter/index.htm
This document contains the release notes for Blk Mem Gen v1.1 which
includes enhancements, resolved issues and outstanding known 
issues.

RELEASE NOTES
=============
This section lists any enhancements, resolved issues and outstanding
known issues.  For further updates and information on the release 
notes, please refer to Solution Record 22304.


1. General Core Design
  1.1 Enhancements
      None at this time. (initial release)

  1.2 Resolved Issues
      None at this time. (initial release)      

  1.3 Outstanding Issues
    1.3.1 GUI doesn't restrict data width ratios when byte-write
          feature is used.
          Change Request: 223314
          When using the byte-writes, no two data widths can have a
	  ratio greater than 4:1.  If the ratio is greater than 4:1, a
	  netlist will not be generated.

    1.3.2 The resource count on the last page of the GUI is only an
          estimation and is not a true indication of the block RAM 
          usage.

    1.3.3 8-bit byte-write will not be supported in v1.1. See 
          datasheet for workaround.

    1.3.4 Core does not generate for large memories.  Depending on the
          machine Coregen runs on, the maximum size of the memory that
          can be generated will vary.  For example, a Dual Pentium-4
          server running at 3.6GHz with 2 Gig RAM can generate a memory 
          core of size 1.8 MBits or 230 K Bytes.

2. General Simulation
  2.1 Enhancements
      None at this time. (initial release)

  2.2 Resolved Issues
      None at this time. (initial release)      

  2.3 Outstanding Issues
    2.3.1 Incorrect output when reset and write operation occur in the
          same clock cycle
          Change Request: 223313
          When a port is configured with "NO_CHANGE" operating mode
          and has a set/reset pin (SSR), the output changes instead of
          adhering to the "NO_CHANGE" operating mode when a set/reset
          and write operation occur in the same clock cycle.
    
    2.3.2 When the 32kx1 primitive is used to build a core, the 
          "NO_CHANGE" operating mode is not supported
          Change request: 223097
          If the 32kx1 primitive is used, when a read is performed on
	  the top 16kx1 RAMB16 followed by a write operation on the
	  bottom 16kx1 RAMB16, the output will change.  Occurs in both
	  behavioral and structural simulations.

    2.3.3 Behavioral models do not flag collision for asymmetric
          read-write ports
          Change request: 223085
          Occurs when the core is configured as a true dual port
          memory, the read data width is much larger than the write
          data width and if any of the operating mode is "NO_CHANGE"
          or "WRITE_FIRST".  When a write operation occurs on both
          ports on the same memory space (no write-write collision)
          that is being read out, the simulation models do not flag a
          write-read collision.  Occurs in both behavioral and 
          structural simulations.
         

3. Documentation
  3.1 Enhancements
      None at this time. (initial release)

  3.2 Resolved Issues
      None at this time. (initial release)

  3.3 Outstanding Issues
      None at this time. (initial release)


TECHNICAL SUPPORT
=================
The fastest method for obtaining specific technical support for the 
Blk Mem Gen core is through the http://support.xilinx.com/ website. 
Questions are routed to a team of engineers with specific 
expertise in using the Blk Mem Gen core.  Xilinx will provide technical 
support for use of this product as described in the Blk Mem Gen Datasheet
Xilinx cannot guarantee timing, functionality, or support of this
product for designs that do not follow these guidelines.