vga_key.twr
来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· TWR 代码 · 共 257 行
TWR
257 行
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Release 8.2.03i Trace
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
F:\Xilinx\bin\nt\trce.exe -ise
F:/basys/basys/huanyizuoyi17/huanyizuoyi/VGAVGA/VGAVGA.ise -intstyle ise -e 3
-l 3 -s 4 -xml vga_key vga_key.ncd -o vga_key.twr vga_key.pcf -ucf vga_key.ucf
Design file: vga_key.ncd
Physical constraint file: vga_key.pcf
Device,speed: xc3s100e,-4 (PRODUCTION 1.26 2006-08-18)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 9.502 ns HIGH 50%;
45876 items analyzed, 32 timing errors detected. (32 setup errors, 0 hold errors)
Minimum period is 10.387ns.
--------------------------------------------------------------------------------
Slack: -0.885ns (requirement - (data path - clock path skew + uncertainty))
Source: m1/m2/addre1[13] (FF)
Destination: m1/m2/green[0] (FF)
Requirement: 9.502ns
Data Path Delay: 10.387ns (Levels of Logic = 9)
Clock Path Skew: 0.000ns
Source Clock: clk_c rising at 0.000ns
Destination Clock: clk_c rising at 9.502ns
Clock Uncertainty: 0.000ns
Data Path: m1/m2/addre1[13] to m1/m2/green[0]
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X24Y20.XQ Tcko 0.592 m1.m2.addre1[13]
m1/m2/addre1[13]
SLICE_X26Y16.G1 net (fanout=9) 1.156 m1.m2.addre1[13]
SLICE_X26Y16.COUT Topcyg 1.131 m1/m2/un1_addre1_2_0.I_10/O
m1/m2/un1_addre1_2_0.I_18
m1/m2/un1_addre1_2_0.I_10
SLICE_X26Y17.CIN net (fanout=1) 0.000 m1/m2/un1_addre1_2_0.I_10/O
SLICE_X26Y17.COUT Tbyp 0.130 m1/m2/un1_addre1_2_0.I_28/O
m1/m2/un1_addre1_2_0.I_19
m1/m2/un1_addre1_2_0.I_28
SLICE_X26Y18.CIN net (fanout=1) 0.000 m1/m2/un1_addre1_2_0.I_28/O
SLICE_X26Y18.COUT Tbyp 0.130 m1/m2/un1_addre1_2_0.I_46/O
m1/m2/un1_addre1_2_0.I_37
m1/m2/un1_addre1_2_0.I_46
SLICE_X26Y19.CIN net (fanout=1) 0.000 m1/m2/un1_addre1_2_0.I_46/O
SLICE_X26Y19.COUT Tbyp 0.130 I_64
m1/m2/un1_addre1_2_0.I_55
m1/m2/un1_addre1_2_0.I_64
SLICE_X18Y13.F1 net (fanout=7) 1.364 I_64
SLICE_X18Y13.X Tilo 0.759 m1/m2/un1_blue168_19_L3
m1/m2/un1_blue168_19_L3
SLICE_X25Y15.F3 net (fanout=3) 0.645 m1/m2/un1_blue168_19_L3
SLICE_X25Y15.X Tilo 0.704 m1/m2/un1_blue168_19_x/O
m1/m2/un1_blue168_19_x
SLICE_X16Y10.G3 net (fanout=1) 0.839 m1/m2/un1_blue168_19_x/O
SLICE_X16Y10.Y Tilo 0.759 m1/m2/green_37_1_iv_4[0]
m1/m2/green_37_0[0]
SLICE_X16Y10.F4 net (fanout=1) 0.023 m1/m2/green_37_0[0]/O
SLICE_X16Y10.X Tilo 0.759 m1/m2/green_37_1_iv_4[0]
m1/m2/green_37_1_iv_4[0]
SLICE_X16Y9.G4 net (fanout=1) 0.374 m1/m2/green_37_1_iv_4[0]
SLICE_X16Y9.CLK Tgck 0.892 green_c[2]
m1/m2/N_203_i
m1/m2/green[0]
------------------------------------------------- ---------------------------
Total 10.387ns (5.986ns logic, 4.401ns route)
(57.6% logic, 42.4% route)
--------------------------------------------------------------------------------
Slack: -0.856ns (requirement - (data path - clock path skew + uncertainty))
Source: m1/m2/addre1[13] (FF)
Destination: m1/m2/blue[1] (FF)
Requirement: 9.502ns
Data Path Delay: 10.358ns (Levels of Logic = 9)
Clock Path Skew: 0.000ns
Source Clock: clk_c rising at 0.000ns
Destination Clock: clk_c rising at 9.502ns
Clock Uncertainty: 0.000ns
Data Path: m1/m2/addre1[13] to m1/m2/blue[1]
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X24Y20.XQ Tcko 0.592 m1.m2.addre1[13]
m1/m2/addre1[13]
SLICE_X26Y16.G1 net (fanout=9) 1.156 m1.m2.addre1[13]
SLICE_X26Y16.COUT Topcyg 1.131 m1/m2/un1_addre1_2_0.I_10/O
m1/m2/un1_addre1_2_0.I_18
m1/m2/un1_addre1_2_0.I_10
SLICE_X26Y17.CIN net (fanout=1) 0.000 m1/m2/un1_addre1_2_0.I_10/O
SLICE_X26Y17.COUT Tbyp 0.130 m1/m2/un1_addre1_2_0.I_28/O
m1/m2/un1_addre1_2_0.I_19
m1/m2/un1_addre1_2_0.I_28
SLICE_X26Y18.CIN net (fanout=1) 0.000 m1/m2/un1_addre1_2_0.I_28/O
SLICE_X26Y18.COUT Tbyp 0.130 m1/m2/un1_addre1_2_0.I_46/O
m1/m2/un1_addre1_2_0.I_37
m1/m2/un1_addre1_2_0.I_46
SLICE_X26Y19.CIN net (fanout=1) 0.000 m1/m2/un1_addre1_2_0.I_46/O
SLICE_X26Y19.COUT Tbyp 0.130 I_64
m1/m2/un1_addre1_2_0.I_55
m1/m2/un1_addre1_2_0.I_64
SLICE_X26Y13.G2 net (fanout=7) 1.596 I_64
SLICE_X26Y13.Y Tilo 0.759 m1.m2.N_203_3
m1/m2/un1_dateb_1
SLICE_X19Y8.G3 net (fanout=13) 1.001 m1.m2.un1_dateb_1
SLICE_X19Y8.Y Tilo 0.704 m1/m2/blue175_L3
m1/m2/un1_blue177_L3
SLICE_X21Y11.G3 net (fanout=1) 0.379 m1/m2/un1_blue177_L3
SLICE_X21Y11.Y Tilo 0.704 m1/m2/N_205_i_1
m1/m2/un1_blue177
SLICE_X17Y10.G2 net (fanout=2) 0.382 m1.m2.N_273
SLICE_X17Y10.Y Tilo 0.704 blue_c[1]
g0_i_a2_1
SLICE_X17Y10.F3 net (fanout=1) 0.023 g0_i_a2_1/O
SLICE_X17Y10.CLK Tfck 0.837 blue_c[1]
g0_i_a2
m1/m2/blue[1]
------------------------------------------------- ---------------------------
Total 10.358ns (5.821ns logic, 4.537ns route)
(56.2% logic, 43.8% route)
--------------------------------------------------------------------------------
Slack: -0.835ns (requirement - (data path - clock path skew + uncertainty))
Source: m1/m2/c[7] (FF)
Destination: m1/m2/green[0] (FF)
Requirement: 9.502ns
Data Path Delay: 10.337ns (Levels of Logic = 7)
Clock Path Skew: 0.000ns
Source Clock: clk_c rising at 0.000ns
Destination Clock: clk_c rising at 9.502ns
Clock Uncertainty: 0.000ns
Data Path: m1/m2/c[7] to m1/m2/green[0]
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X31Y17.XQ Tcko 0.591 m1/m2/c[7]
m1/m2/c[7]
SLICE_X26Y18.G3 net (fanout=3) 1.367 m1/m2/c[7]
SLICE_X26Y18.COUT Topcyg 1.131 m1/m2/un1_addre1_2_0.I_46/O
m1/m2/un1_addre1_2_0.I_54
m1/m2/un1_addre1_2_0.I_46
SLICE_X26Y19.CIN net (fanout=1) 0.000 m1/m2/un1_addre1_2_0.I_46/O
SLICE_X26Y19.COUT Tbyp 0.130 I_64
m1/m2/un1_addre1_2_0.I_55
m1/m2/un1_addre1_2_0.I_64
SLICE_X18Y13.F1 net (fanout=7) 1.364 I_64
SLICE_X18Y13.X Tilo 0.759 m1/m2/un1_blue168_19_L3
m1/m2/un1_blue168_19_L3
SLICE_X25Y15.F3 net (fanout=3) 0.645 m1/m2/un1_blue168_19_L3
SLICE_X25Y15.X Tilo 0.704 m1/m2/un1_blue168_19_x/O
m1/m2/un1_blue168_19_x
SLICE_X16Y10.G3 net (fanout=1) 0.839 m1/m2/un1_blue168_19_x/O
SLICE_X16Y10.Y Tilo 0.759 m1/m2/green_37_1_iv_4[0]
m1/m2/green_37_0[0]
SLICE_X16Y10.F4 net (fanout=1) 0.023 m1/m2/green_37_0[0]/O
SLICE_X16Y10.X Tilo 0.759 m1/m2/green_37_1_iv_4[0]
m1/m2/green_37_1_iv_4[0]
SLICE_X16Y9.G4 net (fanout=1) 0.374 m1/m2/green_37_1_iv_4[0]
SLICE_X16Y9.CLK Tgck 0.892 green_c[2]
m1/m2/N_203_i
m1/m2/green[0]
------------------------------------------------- ---------------------------
Total 10.337ns (5.725ns logic, 4.612ns route)
(55.4% logic, 44.6% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_m2_m1_clkout_c = PERIOD TIMEGRP "m2_m1_clkout_c" 4.148 ns HIGH 50%;
480 items analyzed, 1 timing error detected. (1 setup error, 0 hold errors)
Minimum period is 4.169ns.
--------------------------------------------------------------------------------
Slack: -0.021ns (requirement - (data path - clock path skew + uncertainty))
Source: m2/m2/count3[5] (FF)
Destination: m2/m2/bn3_fast[0] (FF)
Requirement: 4.148ns
Data Path Delay: 4.169ns (Levels of Logic = 2)
Clock Path Skew: 0.000ns
Source Clock: m2/clkout rising at 0.000ns
Destination Clock: m2/clkout rising at 4.148ns
Clock Uncertainty: 0.000ns
Data Path: m2/m2/count3[5] to m2/m2/bn3_fast[0]
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X3Y21.YQ Tcko 0.587 m2/m2/count3[4]
m2/m2/count3[5]
SLICE_X2Y20.F2 net (fanout=2) 0.493 m2/m2/count3[5]
SLICE_X2Y20.X Tilo 0.759 m2/m2/bn324_4
m2/m2/bn324_4
SLICE_X2Y21.F1 net (fanout=1) 0.119 m2/m2/bn324_4
SLICE_X2Y21.X Tilo 0.759 m2/m2/bn324
m2/m2/bn324
SLICE_X13Y23.CE net (fanout=4) 0.897 m2/m2/bn324
SLICE_X13Y23.CLK Tceck 0.555 m2.m2.bn3_fast[0]
m2/m2/bn3_fast[0]
------------------------------------------------- ---------------------------
Total 4.169ns (2.660ns logic, 1.509ns route)
(63.8% logic, 36.2% route)
--------------------------------------------------------------------------------
2 constraints not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 10.387| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 33 Score: 10155
Constraints cover 46356 paths, 0 nets, and 2386 connections
Design statistics:
Minimum period: 10.387ns (Maximum frequency: 96.274MHz)
Analysis completed Sat May 03 16:15:45 2008
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 125 MB
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