📄 vga_key_srr.htm
字号:
<html>
<body><samp><pre>
<!@TC:1209802654>
#Program: Synplify Pro 8.1
#OS: Windows_NT
<a name=compilerReport1>$ Start of Compile
#Sat May 03 16:17:34 2008
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"d:\Program Files\Synplicity\fpga_81\lib\xilinx\unisim.v"
@I::"d:\Program Files\Synplicity\fpga_81\bin\..\lib\xilinx\unisim.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vs_hs.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\sendsave.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\savecon.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\save.v"
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\save.v:66:12:66:25:@N::@XP_MSG">save.v(66)</a><!@TM:1209802663> | Read directive translate_off
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\save.v:127:12:127:24:@N::@XP_MSG">save.v(127)</a><!@TM:1209802663> | Read directive translate_on
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\save.v:130:12:130:21:@W:CS141:@XP_MSG">save.v(130)</a><!@TM:1209802663> | Unrecognized synthesis directive attribute</font>
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\save.v:131:13:131:22:@W:CS141:@XP_MSG">save.v(131)</a><!@TM:1209802663> | Unrecognized synthesis directive attribute</font>
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\save.v:135:13:135:22:@W:CS141:@XP_MSG">save.v(135)</a><!@TM:1209802663> | Unrecognized synthesis directive attribute</font>
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\clkdiv.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\change.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\buttonte.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\key_display.v"
@I::"F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.v"
Verilog syntax check successful!
File F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vs_hs.v changed - recompiling
Selecting top level module vga_key
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vs_hs.v:3:7:3:12:@N::@XP_MSG">vs_hs.v(3)</a><!@TM:1209802663> | Synthesizing module vs_hs
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:3:7:3:14:@N::@XP_MSG">savecon.v(3)</a><!@TM:1209802663> | Synthesizing module savecon
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:127:18:127:19:@N:CG179:@XP_MSG">savecon.v(127)</a><!@TM:1209802663> | Removing redundant assignment
<font color=#A52A2A>@W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:63:0:63:6:@W:CL112:@XP_MSG">savecon.v(63)</a><!@TM:1209802663> | Feedback mux created for signal dateb. Did you forget the set/reset assignment for this signal?</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL190:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Optimizing register bit y[0] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL190:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Optimizing register bit y[1] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL190:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Optimizing register bit y[2] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL190:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Optimizing register bit y[3] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL190:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Optimizing register bit y[4] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL190:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Optimizing register bit z[0] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL190:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Optimizing register bit z[1] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL190:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Optimizing register bit z[2] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL190:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Optimizing register bit z[3] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL190:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Optimizing register bit z[4] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL171:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Pruning Register bit <4> of z[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL171:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Pruning Register bit <3> of z[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL171:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Pruning Register bit <2> of z[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL171:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Pruning Register bit <1> of z[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL171:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Pruning Register bit <0> of z[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL171:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Pruning Register bit <4> of y[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL171:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Pruning Register bit <3> of y[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL171:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Pruning Register bit <2> of y[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL171:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Pruning Register bit <1> of y[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:92:0:92:6:@W:CL171:@XP_MSG">savecon.v(92)</a><!@TM:1209802663> | Pruning Register bit <0> of y[14:0] </font>
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\save.v:40:7:40:11:@N::@XP_MSG">save.v(40)</a><!@TM:1209802663> | Synthesizing module save
<font color=#A52A2A>@W:<a href="@W:CG146:@XP_HELP">CG146</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\save.v:40:7:40:11:@W:CG146:@XP_MSG">save.v(40)</a><!@TM:1209802663> | Creating black box for empty module save</font>
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\sendsave.v:3:7:3:15:@N::@XP_MSG">sendsave.v(3)</a><!@TM:1209802663> | Synthesizing module sendsave
<font color=#A52A2A>@W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\sendsave.v:22:0:22:6:@W:CL112:@XP_MSG">sendsave.v(22)</a><!@TM:1209802663> | Feedback mux created for signal wea. Did you forget the set/reset assignment for this signal?</font>
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vga.v:3:7:3:10:@N::@XP_MSG">vga.v(3)</a><!@TM:1209802663> | Synthesizing module vga
<font color=#A52A2A>@W:<a href="@W:CS148:@XP_HELP">CS148</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vga.v:34:5:34:7:@W:CS148:@XP_MSG">vga.v(34)</a><!@TM:1209802663> | Undriven input dinb, tying to 0</font>
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\clkdiv.v:3:7:3:13:@N::@XP_MSG">clkdiv.v(3)</a><!@TM:1209802663> | Synthesizing module clkdiv
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v:3:7:3:15:@N::@XP_MSG">buttonte.v(3)</a><!@TM:1209802663> | Synthesizing module buttonte
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\change.v:3:7:3:13:@N::@XP_MSG">change.v(3)</a><!@TM:1209802663> | Synthesizing module change
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\key_display.v:3:7:3:18:@N::@XP_MSG">key_display.v(3)</a><!@TM:1209802663> | Synthesizing module key_display
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vga_key.v:3:7:3:14:@N::@XP_MSG">vga_key.v(3)</a><!@TM:1209802663> | Synthesizing module vga_key
@END
Process took 0h:00m:07s realtime, 0h:00m:07s cputime
# Sat May 03 16:17:43 2008
###########################################################[
Version 8.1
<a name=mapperReport2>Synplicity Xilinx Technology Mapper, Version 8.1.0, Build 540R, Built May 9 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Reading constraint file: F:\basys\basys\huanyizuoyi17\huanyizuoyi\VGAVGA\vga_key.sdc
Reading Xilinx I/O pad type table from file <d:\Program Files\Synplicity\fpga_81\lib/xilinx/x_io_tbl.txt>
Reading Xilinx Rocket I/O parameter type table from file <d:\Program Files\Synplicity\fpga_81\lib/xilinx/gttype.txt>
Automatic dissolve at startup in view:work.vga(verilog) of m4(sendsave)
@N:<a href="@N:MF138:@XP_HELP">MF138</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\change.v:66:8:66:12:@N:MF138:@XP_MSG">change.v(66)</a><!@TM:1209802698> | Rom seven_13[6:0] mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\change.v:66:8:66:12:@N:MO106:@XP_MSG">change.v(66)</a><!@TM:1209802698> | Found ROM, 'seven_13[6:0]', 9 words by 7 bits
@N:<a href="@N:MT204:@XP_HELP">MT204</a> : <!@TM:1209802698> | Autoconstrain Mode is ON
RTL optimization done.
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <!@TM:1209802698> | Found 16 bit by 16 bit '==' comparator, 'addre224'
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <!@TM:1209802698> | Found 16 bit by 16 bit '==' comparator, 'y18'
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <!@TM:1209802698> | Found 15 bit by 15 bit '==' comparator, 'un1_addre1_2'
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <!@TM:1209802698> | Found 15 bit by 15 bit '==' comparator, 'un1_addre1_1'
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v:127:1:127:7:@N::@XP_MSG">buttonte.v(127)</a><!@TM:1209802698> | Found counter in view:work.buttonte(verilog) inst count3[8:0]
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v:93:1:93:7:@N::@XP_MSG">buttonte.v(93)</a><!@TM:1209802698> | Found counter in view:work.buttonte(verilog) inst count2[8:0]
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v:58:0:58:6:@N::@XP_MSG">buttonte.v(58)</a><!@TM:1209802698> | Found counter in view:work.buttonte(verilog) inst count1[8:0]
@N: : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v:23:0:23:6:@N::@XP_MSG">buttonte.v(23)</a><!@TM:1209802698> | Found counter in view:work.buttonte(verilog) inst count0[8:0]
Automatic dissolve during optimization of view:work.vga_key(verilog) of m1(vga)
Clock Buffers:
Inserting Clock buffer for port clk, TNM=clk
Inserting Clock buffer on net m2.clkout, TNM=m2_clkout
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:0m:19s -1.90ns 568 / 244
2 0h:0m:19s -1.90ns 568 / 244
3 0h:0m:19s -1.90ns 568 / 244
------------------------------------------------------------
Timing driven replication report
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v:143:0:143:6:@N:FX235:@XP_MSG">buttonte.v(143)</a><!@TM:1209802698> | Instance "m2.m2.bn3[0]" with 5 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:63:0:63:6:@N:FX235:@XP_MSG">savecon.v(63)</a><!@TM:1209802698> | Instance "m1.m2.addre1[2]" with 8 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:63:0:63:6:@N:FX235:@XP_MSG">savecon.v(63)</a><!@TM:1209802698> | Instance "m1.m2.addre1[3]" with 8 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:63:0:63:6:@N:FX235:@XP_MSG">savecon.v(63)</a><!@TM:1209802698> | Instance "m1.m2.addre1[0]" with 8 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:63:0:63:6:@N:FX235:@XP_MSG">savecon.v(63)</a><!@TM:1209802698> | Instance "m1.m2.addre1[1]" with 8 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\buttonte.v:151:4:151:6:@N:FX235:@XP_MSG">buttonte.v(151)</a><!@TM:1209802698> | Instance "m2.m2.bn3_5[0]" with 2 loads has been replicated 1 time(s) to improve timing
Added 5 Registers via timing driven replication
Added 1 LUTs via timing driven replication
Timing driven replication report
No replication required.
Timing driven replication report
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:63:0:63:6:@N:FX235:@XP_MSG">savecon.v(63)</a><!@TM:1209802698> | Instance "m1.m2.addre1[4]" with 8 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:63:0:63:6:@N:FX235:@XP_MSG">savecon.v(63)</a><!@TM:1209802698> | Instance "m1.m2.addre1[7]" with 10 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:63:0:63:6:@N:FX235:@XP_MSG">savecon.v(63)</a><!@TM:1209802698> | Instance "m1.m2.addre1[8]" with 9 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:63:0:63:6:@N:FX235:@XP_MSG">savecon.v(63)</a><!@TM:1209802698> | Instance "m1.m2.addre1[5]" with 9 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\savecon.v:63:0:63:6:@N:FX235:@XP_MSG">savecon.v(63)</a><!@TM:1209802698> | Instance "m1.m2.addre1[6]" with 9 loads has been replicated 1 time(s) to improve timing
Added 5 Registers via timing driven replication
Added 0 LUTs via timing driven replication
Timing driven replication report
No replication required.
Timing driven replication report
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vs_hs.v:16:0:16:6:@N:FX235:@XP_MSG">vs_hs.v(16)</a><!@TM:1209802698> | Instance "m1.m1.countvs[1]" with 5 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vs_hs.v:16:0:16:6:@N:FX235:@XP_MSG">vs_hs.v(16)</a><!@TM:1209802698> | Instance "m1.m1.countvs[2]" with 5 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="f:\basys\basys\huanyizuoyi17\huanyizuoyi\vgavga\vs_hs.v:16:0:16:6:@N:FX235:@XP_MSG">vs_hs.v(16)</a><!@TM:1209802698> | Instance "m1.m1.countvs[3]" with 5 loads has been replicated 1 time(s) to improve timing
Added 3 Registers via timing driven replication
Added 0 LUTs via timing driven replication
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -