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<!@TC:1195174150>
#Program: Synplify Pro 8.1
#OS: Windows_NT
<a name=compilerReport1>$ Start of Compile
#Fri Nov 16 08:49:09 2007
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"d:\Synplicity\fpga_81\lib\xilinx\unisim.v"
@I::"d:\Synplicity\fpga_81\bin\..\lib\xilinx\unisim.v"
@I::"D:\Xilinx\basys\huanyizuoyi\VGAVGA\vs_hs.v"
@I::"D:\Xilinx\basys\huanyizuoyi\VGAVGA\sendsave.v"
@I::"D:\Xilinx\basys\huanyizuoyi\VGAVGA\savecon.v"
@I::"D:\Xilinx\basys\huanyizuoyi\VGAVGA\save.v"
@N: : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\save.v:66:12:66:25:@N::@XP_MSG">save.v(66)</a><!@TM:1195174160> | Read directive translate_off
@N: : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\save.v:127:12:127:24:@N::@XP_MSG">save.v(127)</a><!@TM:1195174160> | Read directive translate_on
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\save.v:130:12:130:21:@W:CS141:@XP_MSG">save.v(130)</a><!@TM:1195174160> | Unrecognized synthesis directive attribute</font>
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\save.v:131:13:131:22:@W:CS141:@XP_MSG">save.v(131)</a><!@TM:1195174160> | Unrecognized synthesis directive attribute</font>
<font color=#A52A2A>@W:<a href="@W:CS141:@XP_HELP">CS141</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\save.v:135:13:135:22:@W:CS141:@XP_MSG">save.v(135)</a><!@TM:1195174160> | Unrecognized synthesis directive attribute</font>
@I::"D:\Xilinx\basys\huanyizuoyi\VGAVGA\vga.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module vga
@N: : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\vs_hs.v:21:7:21:12:@N::@XP_MSG">vs_hs.v(21)</a><!@TM:1195174160> | Synthesizing module vs_hs
@N: : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:21:7:21:14:@N::@XP_MSG">savecon.v(21)</a><!@TM:1195174160> | Synthesizing module savecon
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL169:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register b </font>
<font color=#A52A2A>@W:<a href="@W:CL207:@XP_HELP">CL207</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:201:0:201:6:@W:CL207:@XP_MSG">savecon.v(201)</a><!@TM:1195174160> | All reachable assignments to green[2:0] assign 0, register removed by optimization</font>
<font color=#A52A2A>@W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:78:0:78:6:@W:CL112:@XP_MSG">savecon.v(78)</a><!@TM:1195174160> | Feedback mux created for signal dateb. Did you forget the set/reset assignment for this signal?</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL190:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Optimizing register bit y[0] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL190:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Optimizing register bit y[1] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL190:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Optimizing register bit y[2] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL190:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Optimizing register bit y[3] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL190:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Optimizing register bit y[4] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL190:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Optimizing register bit z[0] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL190:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Optimizing register bit z[1] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL190:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Optimizing register bit z[2] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL190:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Optimizing register bit z[3] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL190:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Optimizing register bit z[4] to a constant 0</font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL171:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register bit <4> of z[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL171:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register bit <3> of z[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL171:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register bit <2> of z[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL171:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register bit <1> of z[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL171:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register bit <0> of z[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL171:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register bit <4> of y[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL171:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register bit <3> of y[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL171:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register bit <2> of y[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL171:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register bit <1> of y[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@W:CL171:@XP_MSG">savecon.v(105)</a><!@TM:1195174160> | Pruning Register bit <0> of y[14:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:201:0:201:6:@W:CL171:@XP_MSG">savecon.v(201)</a><!@TM:1195174160> | Pruning Register bit <2> of red[2:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:201:0:201:6:@W:CL171:@XP_MSG">savecon.v(201)</a><!@TM:1195174160> | Pruning Register bit <1> of red[2:0] </font>
<font color=#A52A2A>@W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:201:0:201:6:@W:CL171:@XP_MSG">savecon.v(201)</a><!@TM:1195174160> | Pruning Register bit <1> of blue[1:0] </font>
@N: : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\save.v:40:7:40:11:@N::@XP_MSG">save.v(40)</a><!@TM:1195174160> | Synthesizing module save
<font color=#A52A2A>@W:<a href="@W:CG146:@XP_HELP">CG146</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\save.v:40:7:40:11:@W:CG146:@XP_MSG">save.v(40)</a><!@TM:1195174160> | Creating black box for empty module save</font>
@N: : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\sendsave.v:21:7:21:15:@N::@XP_MSG">sendsave.v(21)</a><!@TM:1195174160> | Synthesizing module sendsave
<font color=#A52A2A>@W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\sendsave.v:40:0:40:6:@W:CL112:@XP_MSG">sendsave.v(40)</a><!@TM:1195174160> | Feedback mux created for signal wea. Did you forget the set/reset assignment for this signal?</font>
@N: : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\vga.v:21:7:21:10:@N::@XP_MSG">vga.v(21)</a><!@TM:1195174160> | Synthesizing module vga
<font color=#A52A2A>@W:<a href="@W:CS148:@XP_HELP">CS148</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\vga.v:51:5:51:7:@W:CS148:@XP_MSG">vga.v(51)</a><!@TM:1195174160> | Undriven input dinb, tying to 0</font>
@END
Process took 0h:00m:05s realtime, 0h:00m:05s cputime
# Fri Nov 16 08:49:18 2007
###########################################################[
Version 8.1
<a name=mapperReport2>Synplicity Xilinx Technology Mapper, Version 8.1.0, Build 540R, Built May 9 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Reading constraint file: D:\Xilinx\basys\huanyizuoyi\VGAVGA\vga.sdc
Reading Xilinx I/O pad type table from file <d:\Synplicity\fpga_81\lib/xilinx/x_io_tbl.txt>
Reading Xilinx Rocket I/O parameter type table from file <d:\Synplicity\fpga_81\lib/xilinx/gttype.txt>
Automatic dissolve at startup in view:work.vga(verilog) of m4(sendsave)
@N:<a href="@N:MT204:@XP_HELP">MT204</a> : <!@TM:1195174176> | Autoconstrain Mode is ON
RTL optimization done.
@N: : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@N::@XP_MSG">savecon.v(105)</a><!@TM:1195174176> | Found counter in view:work.savecon(verilog) inst n[7:0]
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <!@TM:1195174176> | Found 16 bit by 16 bit '==' comparator, 'z18'
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <!@TM:1195174176> | Found 16 bit by 16 bit '==' comparator, 'z22'
Clock Buffers:
Inserting Clock buffer for port clk, TNM=clk
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:0m:8s 0.00ns 265 / 116
2 0h:0m:8s 1.36ns 265 / 116
------------------------------------------------------------
Timing driven replication report
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\vs_hs.v:34:0:34:6:@N:FX235:@XP_MSG">vs_hs.v(34)</a><!@TM:1195174176> | Instance "m1.countvs[5]" with 6 loads has been replicated 1 time(s) to improve timing
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\vs_hs.v:34:0:34:6:@N:FX235:@XP_MSG">vs_hs.v(34)</a><!@TM:1195174176> | Instance "m1.countvs[4]" with 5 loads has been replicated 1 time(s) to improve timing
Added 2 Registers via timing driven replication
Added 0 LUTs via timing driven replication
Timing driven replication report
@N:<a href="@N:FX235:@XP_HELP">FX235</a> : <a href="d:\xilinx\basys\huanyizuoyi\vgavga\savecon.v:105:0:105:6:@N:FX235:@XP_MSG">savecon.v(105)</a><!@TM:1195174176> | Instance "m2.z[5]" with 4 loads has been replicated 1 time(s) to improve timing
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:0m:10s -0.13ns 283 / 119
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