change.v

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· Verilog 代码 · 共 83 行

`timescale 1ns / 1ps

module change(clkout, rst,bn0,bn1,bn2,bn3, seven, an);
    input clkout;
    input rst;
	 input [3:0] bn0;
	 input [3:0] bn1;
	 input [3:0] bn2;
	 input [3:0] bn3;
    output [6:0] seven;
    output [3:0] an;
	 reg [3:0] seve;
	 reg  [6:0] seven;
	 reg  [3:0] an;
	 reg [1:0] count;
	 

always @(posedge clkout or negedge rst)
 begin 
    if(!rst)
	   count<=0;
	  else
	    count<=count+1;
 end
	 
always @(posedge clkout or negedge rst)
 begin 
    if(!rst)
		  an<=15;
	 else
	   begin
		  case(count)
		   2'd0:an<=4'b1110;
			2'd1:an<=4'b1101;
			2'd2:an<=4'b1011;
			2'd3:an<=4'b0111;
			default:an<=4'b0000;
		  endcase
		end
		
 end
 
always @(posedge clkout or negedge rst)
 begin 
   if(!rst)
	  seve<=0;
	else
	  begin
	   case(an)
		 4'b1110:seve<=bn2;
	    4'b1101:seve<=bn3;
		 4'b1011:seve<=bn0;
		 4'b0111:seve<=bn1;
		 default:seve<=bn0;
		endcase
	  end
 end


always @(posedge clkout or negedge rst)
 begin 
   if(!rst)
	  seven<=0;
	else
	  begin
        case(seve)	 
       4'b0001 : seven <= 8'b1111001;   //1 = F9H
       4'b0010 : seven <= 8'b0100100;   //2 = A4H
       4'b0011 : seven <= 8'b0110000;   //3 = B0H
       4'b0100 : seven <= 8'b0011001;   //4 = 99H
       4'b0101 : seven <= 8'b0010010;   //5 = 92H
       4'b0110 : seven <= 8'b0000010;   //6 = 82H
       4'b0111 : seven <= 8'b1111000;   //7 = F8H
       4'b1000 : seven <= 8'b0000000;   //8 = 80H
       4'b1001 : seven <= 8'b0010000;   //9 = 90H
      
       default : seven <= 8'b1000000;   //0 = C0H
        endcase	
    end
end	 

endmodule