_primary.vhd

这是一个FIFO_Buffer的verilog代码.

library verilog;
use verilog.vl_types.all;
entity t_FIFO_Clock_Domain_Synch is
    generic(
        stack_width     : integer := 32;
        stack_height    : integer := 8;
        stack_ptr_width : integer := 3
    );
end t_FIFO_Clock_Domain_Synch;