small.tan.qmsg

38译码器的设计

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "osc_clk\[0\] 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"osc_clk\[0\]\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "TFFLOP:inst4\|QT TFFLOP:inst4\|QT osc_clk\[0\] 1.311 ns " "Info: Found hold time violation between source  pin or register \"TFFLOP:inst4\|QT\" and destination pin or register \"TFFLOP:inst4\|QT\" for clock \"osc_clk\[0\]\" (Hold time is 1.311 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.921 ns + Largest " "Info: + Largest clock skew is 1.921 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "osc_clk\[0\] destination 9.353 ns + Longest register " "Info: + Longest clock path from clock \"osc_clk\[0\]\" to destination register is 9.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns osc_clk\[0\] 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'osc_clk\[0\]'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { osc_clk[0] } "NODE_NAME" } "" } } { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 256 32 200 272 "osc_clk\[0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns osc_clk\[0\]~clkctrl 2 COMB CLKCTRL_G7 740 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G7; Fanout = 740; COMB Node = 'osc_clk\[0\]~clkctrl'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.139 ns" { osc_clk[0] osc_clk[0]~clkctrl } "NODE_NAME" } "" } } { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 256 32 200 272 "osc_clk\[0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.252 ns) + CELL(0.989 ns) 3.480 ns dividef:inst2\|COUNT\[19\] 3 REG LCFF_X31_Y34_N31 3 " "Info: 3: + IC(1.252 ns) + CELL(0.989 ns) = 3.480 ns; Loc. = LCFF_X31_Y34_N31; Fanout = 3; REG Node = 'dividef:inst2\|COUNT\[19\]'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "2.241 ns" { osc_clk[0]~clkctrl dividef:inst2|COUNT[19] } "NODE_NAME" } "" } } { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.477 ns) + CELL(0.378 ns) 5.335 ns dividef:inst2\|reduce_nor~210 4 COMB LCCOMB_X30_Y35_N14 1 " "Info: 4: + IC(1.477 ns) + CELL(0.378 ns) = 5.335 ns; Loc. = LCCOMB_X30_Y35_N14; Fanout = 1; COMB Node = 'dividef:inst2\|reduce_nor~210'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.855 ns" { dividef:inst2|COUNT[19] dividef:inst2|reduce_nor~210 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.378 ns) 6.056 ns dividef:inst2\|reduce_nor~211 5 COMB LCCOMB_X30_Y35_N8 1 " "Info: 5: + IC(0.343 ns) + CELL(0.378 ns) = 6.056 ns; Loc. = LCCOMB_X30_Y35_N8; Fanout = 1; COMB Node = 'dividef:inst2\|reduce_nor~211'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.721 ns" { dividef:inst2|reduce_nor~210 dividef:inst2|reduce_nor~211 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.342 ns) + CELL(0.378 ns) 6.776 ns dividef:inst2\|reduce_nor~0 6 COMB LCCOMB_X30_Y35_N4 14 " "Info: 6: + IC(0.342 ns) + CELL(0.378 ns) = 6.776 ns; Loc. = LCCOMB_X30_Y35_N4; Fanout = 14; COMB Node = 'dividef:inst2\|reduce_nor~0'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.720 ns" { dividef:inst2|reduce_nor~211 dividef:inst2|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.000 ns) 7.492 ns dividef:inst2\|reduce_nor~0clkctrl 7 COMB CLKCTRL_G9 2 " "Info: 7: + IC(0.716 ns) + CELL(0.000 ns) = 7.492 ns; Loc. = CLKCTRL_G9; Fanout = 2; COMB Node = 'dividef:inst2\|reduce_nor~0clkctrl'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.716 ns" { dividef:inst2|reduce_nor~0 dividef:inst2|reduce_nor~0clkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.679 ns) 9.353 ns TFFLOP:inst4\|QT 8 REG LCFF_X34_Y26_N1 3 " "Info: 8: + IC(1.182 ns) + CELL(0.679 ns) = 9.353 ns; Loc. = LCFF_X34_Y26_N1; Fanout = 3; REG Node = 'TFFLOP:inst4\|QT'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.861 ns" { dividef:inst2|reduce_nor~0clkctrl TFFLOP:inst4|QT } "NODE_NAME" } "" } } { "TFFLOP.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/TFFLOP.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.902 ns 41.72 % " "Info: Total cell delay = 3.902 ns ( 41.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.451 ns 58.28 % " "Info: Total interconnect delay = 5.451 ns ( 58.28 % )" {  } {  } 0}  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "9.353 ns" { osc_clk[0] osc_clk[0]~clkctrl dividef:inst2|COUNT[19] dividef:inst2|reduce_nor~210 dividef:inst2|reduce_nor~211 dividef:inst2|reduce_nor~0 dividef:inst2|reduce_nor~0clkctrl TFFLOP:inst4|QT } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.353 ns" { osc_clk[0] osc_clk[0]~combout osc_clk[0]~clkctrl dividef:inst2|COUNT[19] dividef:inst2|reduce_nor~210 dividef:inst2|reduce_nor~211 dividef:inst2|reduce_nor~0 dividef:inst2|reduce_nor~0clkctrl TFFLOP:inst4|QT } { 0.0ns 0.0ns 0.139ns 1.252ns 1.477ns 0.343ns 0.342ns 0.716ns 1.182ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.378ns 0.378ns 0.378ns 0.0ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "osc_clk\[0\] source 7.432 ns - Shortest register " "Info: - Shortest clock path from clock \"osc_clk\[0\]\" to source register is 7.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns osc_clk\[0\] 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'osc_clk\[0\]'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { osc_clk[0] } "NODE_NAME" } "" } } { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 256 32 200 272 "osc_clk\[0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns osc_clk\[0\]~clkctrl 2 COMB CLKCTRL_G7 740 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G7; Fanout = 740; COMB Node = 'osc_clk\[0\]~clkctrl'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.139 ns" { osc_clk[0] osc_clk[0]~clkctrl } "NODE_NAME" } "" } } { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 256 32 200 272 "osc_clk\[0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.253 ns) + CELL(0.989 ns) 3.481 ns dividef:inst2\|COUNT\[0\] 3 REG LCFF_X30_Y35_N25 3 " "Info: 3: + IC(1.253 ns) + CELL(0.989 ns) = 3.481 ns; Loc. = LCFF_X30_Y35_N25; Fanout = 3; REG Node = 'dividef:inst2\|COUNT\[0\]'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "2.242 ns" { osc_clk[0]~clkctrl dividef:inst2|COUNT[0] } "NODE_NAME" } "" } } { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.378 ns) 4.291 ns dividef:inst2\|reduce_nor~216 4 COMB LCCOMB_X30_Y35_N0 1 " "Info: 4: + IC(0.432 ns) + CELL(0.378 ns) = 4.291 ns; Loc. = LCCOMB_X30_Y35_N0; Fanout = 1; COMB Node = 'dividef:inst2\|reduce_nor~216'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.810 ns" { dividef:inst2|COUNT[0] dividef:inst2|reduce_nor~216 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.210 ns) 4.855 ns dividef:inst2\|reduce_nor~0 5 COMB LCCOMB_X30_Y35_N4 14 " "Info: 5: + IC(0.354 ns) + CELL(0.210 ns) = 4.855 ns; Loc. = LCCOMB_X30_Y35_N4; Fanout = 14; COMB Node = 'dividef:inst2\|reduce_nor~0'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.564 ns" { dividef:inst2|reduce_nor~216 dividef:inst2|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.000 ns) 5.571 ns dividef:inst2\|reduce_nor~0clkctrl 6 COMB CLKCTRL_G9 2 " "Info: 6: + IC(0.716 ns) + CELL(0.000 ns) = 5.571 ns; Loc. = CLKCTRL_G9; Fanout = 2; COMB Node = 'dividef:inst2\|reduce_nor~0clkctrl'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.716 ns" { dividef:inst2|reduce_nor~0 dividef:inst2|reduce_nor~0clkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.679 ns) 7.432 ns TFFLOP:inst4\|QT 7 REG LCFF_X34_Y26_N1 3 " "Info: 7: + IC(1.182 ns) + CELL(0.679 ns) = 7.432 ns; Loc. = LCFF_X34_Y26_N1; Fanout = 3; REG Node = 'TFFLOP:inst4\|QT'" {  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.861 ns" { dividef:inst2|reduce_nor~0clkctrl TFFLOP:inst4|QT } "NODE_NAME" } "" } } { "TFFLOP.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/TFFLOP.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.356 ns 45.16 % " "Info: Total cell delay = 3.356 ns ( 45.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.076 ns 54.84 % " "Info: Total interconnect delay = 4.076 ns ( 54.84 % )" {  } {  } 0}  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "7.432 ns" { osc_clk[0] osc_clk[0]~clkctrl dividef:inst2|COUNT[0] dividef:inst2|reduce_nor~216 dividef:inst2|reduce_nor~0 dividef:inst2|reduce_nor~0clkctrl TFFLOP:inst4|QT } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.432 ns" { osc_clk[0] osc_clk[0]~combout osc_clk[0]~clkctrl dividef:inst2|COUNT[0] dividef:inst2|reduce_nor~216 dividef:inst2|reduce_nor~0 dividef:inst2|reduce_nor~0clkctrl TFFLOP:inst4|QT } { 0.0ns 0.0ns 0.139ns 1.253ns 0.432ns 0.354ns 0.716ns 1.182ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.378ns 0.21ns 0.0ns 0.679ns } } }  } 0}  } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "9.353 ns" { osc_clk[0] osc_clk[0]~clkctrl dividef:inst2|COUNT[19] dividef:inst2|reduce_nor~210 dividef:inst2|reduce_nor~211 dividef:inst2|reduce_nor~0 dividef:inst2|reduce_nor~0clkctrl TFFLOP:inst4|QT } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.353 ns" { osc_clk[0] osc_clk[0]~combout osc_clk[0]~clkctrl dividef:inst2|COUNT[19] dividef:inst2|reduce_nor~210 dividef:inst2|reduce_nor~211 dividef:inst2|reduce_nor~0 dividef:inst2|reduce_nor~0clkctrl TFFLOP:inst4|QT } { 0.0ns 0.0ns 0.139ns 1.252ns 1.477ns 0.343ns 0.342ns 0.716ns 1.182ns } { 0.0ns 1.1ns 0.0ns 0.989ns 0.378ns 0.378ns 0.378ns 0.0ns 0.679ns } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V