📄 small.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "34 " "Warning: Found 34 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[8\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[8\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[8\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[5\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[5\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[5\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[7\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[7\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[7\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[6\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[6\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[6\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[3\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[3\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[3\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[1\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[1\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[1\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[4\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[4\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[4\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[2\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[2\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[2\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[23\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[23\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[23\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[24\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[24\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[24\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[17\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[17\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[17\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[19\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[19\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[19\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[18\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[18\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[18\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[20\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[20\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[20\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "dividef:inst2\|reduce_nor~214 " "Info: Detected gated clock \"dividef:inst2\|reduce_nor~214\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|reduce_nor~214" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[0\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[0\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[0\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[25\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[25\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[25\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "dividef:inst2\|reduce_nor~215 " "Info: Detected gated clock \"dividef:inst2\|reduce_nor~215\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|reduce_nor~215" } } } } } 0} { "Info" "ITAN_GATED_CLK" "dividef:inst2\|reduce_nor~209 " "Info: Detected gated clock \"dividef:inst2\|reduce_nor~209\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|reduce_nor~209" } } } } } 0} { "Info" "ITAN_GATED_CLK" "dividef:inst2\|reduce_nor~210 " "Info: Detected gated clock \"dividef:inst2\|reduce_nor~210\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|reduce_nor~210" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[22\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[22\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[22\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[21\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[21\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[21\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[11\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[11\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[11\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[12\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[12\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[12\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[9\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[9\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[9\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[10\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[10\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[10\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[13\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[13\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[13\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[15\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[15\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[15\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[16\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[16\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[16\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "dividef:inst2\|COUNT\[14\] " "Info: Detected ripple clock \"dividef:inst2\|COUNT\[14\]\" as buffer" { } { { "dividef.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/dividef.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|COUNT\[14\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "dividef:inst2\|reduce_nor~216 " "Info: Detected gated clock \"dividef:inst2\|reduce_nor~216\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|reduce_nor~216" } } } } } 0} { "Info" "ITAN_GATED_CLK" "dividef:inst2\|reduce_nor~211 " "Info: Detected gated clock \"dividef:inst2\|reduce_nor~211\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|reduce_nor~211" } } } } } 0} { "Info" "ITAN_GATED_CLK" "dividef:inst2\|reduce_nor~213 " "Info: Detected gated clock \"dividef:inst2\|reduce_nor~213\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|reduce_nor~213" } } } } } 0} { "Info" "ITAN_GATED_CLK" "dividef:inst2\|reduce_nor~212 " "Info: Detected gated clock \"dividef:inst2\|reduce_nor~212\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dividef:inst2\|reduce_nor~212" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "osc_clk\[0\] register small_2C35:inst\|cpu:the_cpu\|R_logic_op\[1\] register small_2C35:inst\|cpu:the_cpu\|W_cmp_result 125.93 MHz 7.941 ns Internal " "Info: Clock \"osc_clk\[0\]\" has Internal fmax of 125.93 MHz between source register \"small_2C35:inst\|cpu:the_cpu\|R_logic_op\[1\]\" and destination register \"small_2C35:inst\|cpu:the_cpu\|W_cmp_result\" (period= 7.941 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.659 ns + Longest register register " "Info: + Longest register to register delay is 7.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns small_2C35:inst\|cpu:the_cpu\|R_logic_op\[1\] 1 REG LCFF_X30_Y14_N5 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y14_N5; Fanout = 32; REG Node = 'small_2C35:inst\|cpu:the_cpu\|R_logic_op\[1\]'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { small_2C35:inst|cpu:the_cpu|R_logic_op[1] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 681 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.316 ns) + CELL(0.664 ns) 1.980 ns small_2C35:inst\|cpu:the_cpu\|E_logic_result\[21\]~4767 2 COMB LCCOMB_X29_Y11_N18 2 " "Info: 2: + IC(1.316 ns) + CELL(0.664 ns) = 1.980 ns; Loc. = LCCOMB_X29_Y11_N18; Fanout = 2; COMB Node = 'small_2C35:inst\|cpu:the_cpu\|E_logic_result\[21\]~4767'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.980 ns" { small_2C35:inst|cpu:the_cpu|R_logic_op[1] small_2C35:inst|cpu:the_cpu|E_logic_result[21]~4767 } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 448 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.117 ns) + CELL(0.210 ns) 3.307 ns small_2C35:inst\|cpu:the_cpu\|reduce_nor~2804 3 COMB LCCOMB_X30_Y13_N0 1 " "Info: 3: + IC(1.117 ns) + CELL(0.210 ns) = 3.307 ns; Loc. = LCCOMB_X30_Y13_N0; Fanout = 1; COMB Node = 'small_2C35:inst\|cpu:the_cpu\|reduce_nor~2804'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.327 ns" { small_2C35:inst|cpu:the_cpu|E_logic_result[21]~4767 small_2C35:inst|cpu:the_cpu|reduce_nor~2804 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.049 ns) + CELL(0.378 ns) 4.734 ns small_2C35:inst\|cpu:the_cpu\|reduce_nor~2805 4 COMB LCCOMB_X27_Y14_N24 1 " "Info: 4: + IC(1.049 ns) + CELL(0.378 ns) = 4.734 ns; Loc. = LCCOMB_X27_Y14_N24; Fanout = 1; COMB Node = 'small_2C35:inst\|cpu:the_cpu\|reduce_nor~2805'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.427 ns" { small_2C35:inst|cpu:the_cpu|reduce_nor~2804 small_2C35:inst|cpu:the_cpu|reduce_nor~2805 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.378 ns) 6.152 ns small_2C35:inst\|cpu:the_cpu\|reduce_nor~125 5 COMB LCCOMB_X27_Y12_N24 1 " "Info: 5: + IC(1.040 ns) + CELL(0.378 ns) = 6.152 ns; Loc. = LCCOMB_X27_Y12_N24; Fanout = 1; COMB Node = 'small_2C35:inst\|cpu:the_cpu\|reduce_nor~125'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.418 ns" { small_2C35:inst|cpu:the_cpu|reduce_nor~2805 small_2C35:inst|cpu:the_cpu|reduce_nor~125 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.019 ns) + CELL(0.378 ns) 7.549 ns small_2C35:inst\|cpu:the_cpu\|E_cmp_result~94 6 COMB LCCOMB_X30_Y12_N28 1 " "Info: 6: + IC(1.019 ns) + CELL(0.378 ns) = 7.549 ns; Loc. = LCCOMB_X30_Y12_N28; Fanout = 1; COMB Node = 'small_2C35:inst\|cpu:the_cpu\|E_cmp_result~94'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.397 ns" { small_2C35:inst|cpu:the_cpu|reduce_nor~125 small_2C35:inst|cpu:the_cpu|E_cmp_result~94 } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 443 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 7.659 ns small_2C35:inst\|cpu:the_cpu\|W_cmp_result 7 REG LCFF_X30_Y12_N29 2 " "Info: 7: + IC(0.000 ns) + CELL(0.110 ns) = 7.659 ns; Loc. = LCFF_X30_Y12_N29; Fanout = 2; REG Node = 'small_2C35:inst\|cpu:the_cpu\|W_cmp_result'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.110 ns" { small_2C35:inst|cpu:the_cpu|E_cmp_result~94 small_2C35:inst|cpu:the_cpu|W_cmp_result } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 699 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.118 ns 27.65 % " "Info: Total cell delay = 2.118 ns ( 27.65 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.541 ns 72.35 % " "Info: Total interconnect delay = 5.541 ns ( 72.35 % )" { } { } 0} } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "7.659 ns" { small_2C35:inst|cpu:the_cpu|R_logic_op[1] small_2C35:inst|cpu:the_cpu|E_logic_result[21]~4767 small_2C35:inst|cpu:the_cpu|reduce_nor~2804 small_2C35:inst|cpu:the_cpu|reduce_nor~2805 small_2C35:inst|cpu:the_cpu|reduce_nor~125 small_2C35:inst|cpu:the_cpu|E_cmp_result~94 small_2C35:inst|cpu:the_cpu|W_cmp_result } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.659 ns" { small_2C35:inst|cpu:the_cpu|R_logic_op[1] small_2C35:inst|cpu:the_cpu|E_logic_result[21]~4767 small_2C35:inst|cpu:the_cpu|reduce_nor~2804 small_2C35:inst|cpu:the_cpu|reduce_nor~2805 small_2C35:inst|cpu:the_cpu|reduce_nor~125 small_2C35:inst|cpu:the_cpu|E_cmp_result~94 small_2C35:inst|cpu:the_cpu|W_cmp_result } { 0.000ns 1.316ns 1.117ns 1.049ns 1.040ns 1.019ns 0.000ns } { 0.000ns 0.664ns 0.210ns 0.378ns 0.378ns 0.378ns 0.110ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns - Smallest " "Info: - Smallest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "osc_clk\[0\] destination 3.147 ns + Shortest register " "Info: + Shortest clock path from clock \"osc_clk\[0\]\" to destination register is 3.147 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns osc_clk\[0\] 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'osc_clk\[0\]'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { osc_clk[0] } "NODE_NAME" } "" } } { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 256 32 200 272 "osc_clk\[0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns osc_clk\[0\]~clkctrl 2 COMB CLKCTRL_G7 740 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G7; Fanout = 740; COMB Node = 'osc_clk\[0\]~clkctrl'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.139 ns" { osc_clk[0] osc_clk[0]~clkctrl } "NODE_NAME" } "" } } { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 256 32 200 272 "osc_clk\[0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.229 ns) + CELL(0.679 ns) 3.147 ns small_2C35:inst\|cpu:the_cpu\|W_cmp_result 3 REG LCFF_X30_Y12_N29 2 " "Info: 3: + IC(1.229 ns) + CELL(0.679 ns) = 3.147 ns; Loc. = LCFF_X30_Y12_N29; Fanout = 2; REG Node = 'small_2C35:inst\|cpu:the_cpu\|W_cmp_result'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.908 ns" { osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|W_cmp_result } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 699 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 56.53 % " "Info: Total cell delay = 1.779 ns ( 56.53 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.368 ns 43.47 % " "Info: Total interconnect delay = 1.368 ns ( 43.47 % )" { } { } 0} } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "3.147 ns" { osc_clk[0] osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|W_cmp_result } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.147 ns" { osc_clk[0] osc_clk[0]~combout osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|W_cmp_result } { 0.000ns 0.000ns 0.139ns 1.229ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "osc_clk\[0\] source 3.159 ns - Longest register " "Info: - Longest clock path from clock \"osc_clk\[0\]\" to source register is 3.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns osc_clk\[0\] 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'osc_clk\[0\]'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { osc_clk[0] } "NODE_NAME" } "" } } { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 256 32 200 272 "osc_clk\[0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns osc_clk\[0\]~clkctrl 2 COMB CLKCTRL_G7 740 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G7; Fanout = 740; COMB Node = 'osc_clk\[0\]~clkctrl'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.139 ns" { osc_clk[0] osc_clk[0]~clkctrl } "NODE_NAME" } "" } } { "small.bdf" "" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 256 32 200 272 "osc_clk\[0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.241 ns) + CELL(0.679 ns) 3.159 ns small_2C35:inst\|cpu:the_cpu\|R_logic_op\[1\] 3 REG LCFF_X30_Y14_N5 32 " "Info: 3: + IC(1.241 ns) + CELL(0.679 ns) = 3.159 ns; Loc. = LCFF_X30_Y14_N5; Fanout = 32; REG Node = 'small_2C35:inst\|cpu:the_cpu\|R_logic_op\[1\]'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.920 ns" { osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|R_logic_op[1] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 681 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 56.32 % " "Info: Total cell delay = 1.779 ns ( 56.32 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.380 ns 43.68 % " "Info: Total interconnect delay = 1.380 ns ( 43.68 % )" { } { } 0} } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "3.159 ns" { osc_clk[0] osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|R_logic_op[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.159 ns" { osc_clk[0] osc_clk[0]~combout osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|R_logic_op[1] } { 0.000ns 0.000ns 0.139ns 1.241ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } } 0} } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "3.147 ns" { osc_clk[0] osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|W_cmp_result } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.147 ns" { osc_clk[0] osc_clk[0]~combout osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|W_cmp_result } { 0.000ns 0.000ns 0.139ns 1.229ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "3.159 ns" { osc_clk[0] osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|R_logic_op[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.159 ns" { osc_clk[0] osc_clk[0]~combout osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|R_logic_op[1] } { 0.000ns 0.000ns 0.139ns 1.241ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" { } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 681 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 699 -1 0 } } } 0} } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "7.659 ns" { small_2C35:inst|cpu:the_cpu|R_logic_op[1] small_2C35:inst|cpu:the_cpu|E_logic_result[21]~4767 small_2C35:inst|cpu:the_cpu|reduce_nor~2804 small_2C35:inst|cpu:the_cpu|reduce_nor~2805 small_2C35:inst|cpu:the_cpu|reduce_nor~125 small_2C35:inst|cpu:the_cpu|E_cmp_result~94 small_2C35:inst|cpu:the_cpu|W_cmp_result } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.659 ns" { small_2C35:inst|cpu:the_cpu|R_logic_op[1] small_2C35:inst|cpu:the_cpu|E_logic_result[21]~4767 small_2C35:inst|cpu:the_cpu|reduce_nor~2804 small_2C35:inst|cpu:the_cpu|reduce_nor~2805 small_2C35:inst|cpu:the_cpu|reduce_nor~125 small_2C35:inst|cpu:the_cpu|E_cmp_result~94 small_2C35:inst|cpu:the_cpu|W_cmp_result } { 0.000ns 1.316ns 1.117ns 1.049ns 1.040ns 1.019ns 0.000ns } { 0.000ns 0.664ns 0.210ns 0.378ns 0.378ns 0.378ns 0.110ns } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "3.147 ns" { osc_clk[0] osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|W_cmp_result } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.147 ns" { osc_clk[0] osc_clk[0]~combout osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|W_cmp_result } { 0.000ns 0.000ns 0.139ns 1.229ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "3.159 ns" { osc_clk[0] osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|R_logic_op[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.159 ns" { osc_clk[0] osc_clk[0]~combout osc_clk[0]~clkctrl small_2C35:inst|cpu:the_cpu|R_logic_op[1] } { 0.000ns 0.000ns 0.139ns 1.241ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] register sld_hub:sld_hub_inst\|hub_tdo 130.68 MHz 7.652 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 130.68 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 7.652 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.556 ns + Longest register register " "Info: + Longest register to register delay is 3.556 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 1 REG LCFF_X32_Y25_N9 64 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y25_N9; Fanout = 64; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.803 ns) + CELL(0.664 ns) 1.467 ns sld_hub:sld_hub_inst\|hub_tdo~442 2 COMB LCCOMB_X32_Y25_N26 1 " "Info: 2: + IC(0.803 ns) + CELL(0.664 ns) = 1.467 ns; Loc. = LCCOMB_X32_Y25_N26; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~442'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.467 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~442 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.755 ns) + CELL(0.664 ns) 2.886 ns sld_hub:sld_hub_inst\|hub_tdo~445 3 COMB LCCOMB_X31_Y25_N22 1 " "Info: 3: + IC(0.755 ns) + CELL(0.664 ns) = 2.886 ns; Loc. = LCCOMB_X31_Y25_N22; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~445'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.419 ns" { sld_hub:sld_hub_inst|hub_tdo~442 sld_hub:sld_hub_inst|hub_tdo~445 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.350 ns) + CELL(0.210 ns) 3.446 ns sld_hub:sld_hub_inst\|hub_tdo~447 4 COMB LCCOMB_X31_Y25_N6 1 " "Info: 4: + IC(0.350 ns) + CELL(0.210 ns) = 3.446 ns; Loc. = LCCOMB_X31_Y25_N6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~447'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.560 ns" { sld_hub:sld_hub_inst|hub_tdo~445 sld_hub:sld_hub_inst|hub_tdo~447 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 3.556 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LCFF_X31_Y25_N7 1 " "Info: 5: + IC(0.000 ns) + CELL(0.110 ns) = 3.556 ns; Loc. = LCFF_X31_Y25_N7; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.110 ns" { sld_hub:sld_hub_inst|hub_tdo~447 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.648 ns 46.34 % " "Info: Total cell delay = 1.648 ns ( 46.34 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.908 ns 53.66 % " "Info: Total interconnect delay = 1.908 ns ( 53.66 % )" { } { } 0} } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "3.556 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~442 sld_hub:sld_hub_inst|hub_tdo~445 sld_hub:sld_hub_inst|hub_tdo~447 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.556 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~442 sld_hub:sld_hub_inst|hub_tdo~445 sld_hub:sld_hub_inst|hub_tdo~447 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.803ns 0.755ns 0.350ns 0.000ns } { 0.000ns 0.664ns 0.664ns 0.210ns 0.110ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 1.905 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 1.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 221 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G3; Fanout = 221; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.679 ns) 1.905 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X31_Y25_N7 1 " "Info: 3: + IC(1.226 ns) + CELL(0.679 ns) = 1.905 ns; Loc. = LCFF_X31_Y25_N7; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.905 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 35.64 % " "Info: Total cell delay = 0.679 ns ( 35.64 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.226 ns 64.36 % " "Info: Total interconnect delay = 1.226 ns ( 64.36 % )" { } { } 0} } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.226ns } { 0.000ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 1.905 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 1.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 221 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G3; Fanout = 221; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.679 ns) 1.905 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 3 REG LCFF_X32_Y25_N9 64 " "Info: 3: + IC(1.226 ns) + CELL(0.679 ns) = 1.905 ns; Loc. = LCFF_X32_Y25_N9; Fanout = 64; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" { } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.905 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 35.64 % " "Info: Total cell delay = 0.679 ns ( 35.64 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.226 ns 64.36 % " "Info: Total interconnect delay = 1.226 ns ( 64.36 % )" { } { } 0} } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 0.000ns 1.226ns } { 0.000ns 0.000ns 0.679ns } } } } 0} } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.226ns } { 0.000ns 0.000ns 0.679ns } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 0.000ns 1.226ns } { 0.000ns 0.000ns 0.679ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" { } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} } { { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "3.556 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~442 sld_hub:sld_hub_inst|hub_tdo~445 sld_hub:sld_hub_inst|hub_tdo~447 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.556 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~442 sld_hub:sld_hub_inst|hub_tdo~445 sld_hub:sld_hub_inst|hub_tdo~447 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.803ns 0.755ns 0.350ns 0.000ns } { 0.000ns 0.664ns 0.664ns 0.210ns 0.110ns } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 0.000ns 1.226ns } { 0.000ns 0.000ns 0.679ns } } } { "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" "" { Report "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small_cmp.qrpt" Compiler "small" "UNKNOWN" "V1" "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/small.quartus_db" { Floorplan "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/" "" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.905 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 0.000ns 1.226ns } { 0.000ns 0.000ns 0.679ns } } } } 0}
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