small.map.qmsg

38译码器的设计

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpchain " "Info: Found entity 1: cmpchain" {  } { { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 84 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_acquisition_buffer-rtl " "Info: Found design unit 1: sld_acquisition_buffer-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 73 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_offload_buffer_mgr-rtl " "Info: Found design unit 2: sld_offload_buffer_mgr-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 308 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_acquisition_buffer " "Info: Found entity 1: sld_acquisition_buffer" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 46 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_offload_buffer_mgr " "Info: Found entity 2: sld_offload_buffer_mgr" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 271 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_n5a.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_n5a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_n5a " "Info: Found entity 1: cntr_n5a" {  } { { "db/cntr_n5a.tdf" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/cntr_n5a.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ff " "Info: Found entity 1: lpm_ff" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" 46 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jm92.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_jm92.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jm92 " "Info: Found entity 1: altsyncram_jm92" {  } { { "db/altsyncram_jm92.tdf" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/altsyncram_jm92.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_c58.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_c58.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_c58 " "Info: Found entity 1: cntr_c58" {  } { { "db/cntr_c58.tdf" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/cntr_c58.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_dv7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_dv7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_dv7 " "Info: Found entity 1: cntr_dv7" {  } { { "db/cntr_dv7.tdf" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/cntr_dv7.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" { { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|CLR acq_trigger_in\[0\] " "Info: Source node \"\|small\|CLR\" connects to port \"acq_trigger_in\[0\]\"" {  } { { "small.bdf" "CLR" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 544 72 240 560 "CLR" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|CLR acq_data_in\[0\] " "Info: Source node \"\|small\|CLR\" connects to port \"acq_data_in\[0\]\"" {  } { { "small.bdf" "CLR" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 544 72 240 560 "CLR" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|D acq_trigger_in\[1\] " "Info: Source node \"\|small\|D\" connects to port \"acq_trigger_in\[1\]\"" {  } { { "small.bdf" "D" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 512 72 240 528 "D" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|D acq_data_in\[1\] " "Info: Source node \"\|small\|D\" connects to port \"acq_data_in\[1\]\"" {  } { { "small.bdf" "D" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 512 72 240 528 "D" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|PSET acq_trigger_in\[2\] " "Info: Source node \"\|small\|PSET\" connects to port \"acq_trigger_in\[2\]\"" {  } { { "small.bdf" "PSET" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 560 72 240 576 "PSET" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|PSET acq_data_in\[2\] " "Info: Source node \"\|small\|PSET\" connects to port \"acq_data_in\[2\]\"" {  } { { "small.bdf" "PSET" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 560 72 240 576 "PSET" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|Q acq_trigger_in\[3\] " "Info: Source node \"\|small\|Q\" connects to port \"acq_trigger_in\[3\]\"" {  } { { "small.bdf" "Q" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 512 528 704 528 "Q" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|Q acq_data_in\[3\] " "Info: Source node \"\|small\|Q\" connects to port \"acq_data_in\[3\]\"" {  } { { "small.bdf" "Q" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 512 528 704 528 "Q" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|QT acq_trigger_in\[4\] " "Info: Source node \"\|small\|QT\" connects to port \"acq_trigger_in\[4\]\"" {  } { { "small.bdf" "QT" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 608 600 857 624 "QT" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|QT acq_data_in\[4\] " "Info: Source node \"\|small\|QT\" connects to port \"acq_data_in\[4\]\"" {  } { { "small.bdf" "QT" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 608 600 857 624 "QT" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|small\|osc_clk\[0\] acq_clk " "Info: Source node \"\|small\|osc_clk\[0\]\" connects to port \"acq_clk\"" {  } { { "small.bdf" "osc_clk\[0\]" { Schematic "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small.bdf" { { 256 32 200 272 "osc_clk\[0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_rpe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_rpe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_rpe " "Info: Found entity 1: decode_rpe" {  } { { "db/decode_rpe.tdf" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/decode_rpe.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|onchip_ram_s1_arbitrator:the_onchip_ram_s1\|d1_reasons_to_wait data_in GND " "Warning: Reduced register \"small_2C35:inst\|onchip_ram_s1_arbitrator:the_onchip_ram_s1\|d1_reasons_to_wait\" with stuck data_in port to stuck value GND" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 490 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ienable_reg\[0\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ienable_reg\[0\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 704 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[31\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[31\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[30\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[30\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[29\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[29\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[28\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[28\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[27\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[27\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[26\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[26\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[25\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[25\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[24\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[24\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[23\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[23\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[22\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[22\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[21\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[21\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[20\] data_in GND " "Warning: Reduced register \"small_2C35:inst\|cpu:the_cpu\|W_ipending_reg\[20\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 706 -1 0 } }  } 0}