small.map.qmsg

38译码器的设计

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_8_is_x cpu_test_bench.vhd(218) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(218): object \"av_ld_data_aligned_unfiltered_8_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 218 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_9_is_x cpu_test_bench.vhd(219) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(219): object \"av_ld_data_aligned_unfiltered_9_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 219 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "cpu_test_bench.vhd(234) " "Warning: (10037) Verilog HDL or VHDL warning at cpu_test_bench.vhd(234): condition expression evaluates to a constant" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 234 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_rf_module small_2C35:inst\|cpu:the_cpu\|cpu_rf_module:cpu_rf " "Info: Elaborating entity \"cpu_rf_module\" for hierarchy \"small_2C35:inst\|cpu:the_cpu\|cpu_rf_module:cpu_rf\"" {  } { { "cpu.vhd" "cpu_rf" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 1261 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram small_2C35:inst\|cpu:the_cpu\|cpu_rf_module:cpu_rf\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"small_2C35:inst\|cpu:the_cpu\|cpu_rf_module:cpu_rf\|altsyncram:the_altsyncram\"" {  } { { "cpu.vhd" "the_altsyncram" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu.vhd" 98 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vuo1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vuo1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vuo1 " "Info: Found entity 1: altsyncram_vuo1" {  } { { "db/altsyncram_vuo1.tdf" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/altsyncram_vuo1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_vuo1 small_2C35:inst\|cpu:the_cpu\|cpu_rf_module:cpu_rf\|altsyncram:the_altsyncram\|altsyncram_vuo1:auto_generated " "Info: Elaborating entity \"altsyncram_vuo1\" for hierarchy \"small_2C35:inst\|cpu:the_cpu\|cpu_rf_module:cpu_rf\|altsyncram:the_altsyncram\|altsyncram_vuo1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led_pio_s1_arbitrator small_2C35:inst\|led_pio_s1_arbitrator:the_led_pio_s1 " "Info: Elaborating entity \"led_pio_s1_arbitrator\" for hierarchy \"small_2C35:inst\|led_pio_s1_arbitrator:the_led_pio_s1\"" {  } { { "small_2C35.vhd" "the_led_pio_s1" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 1177 -1 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "cpu_data_master_read_data_valid_led_pio_s1 small_2C35.vhd(261) " "Warning: Output port \"cpu_data_master_read_data_valid_led_pio_s1\" at small_2C35.vhd(261) has no driver" {  } { { "small_2C35.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 261 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "led_pio.vhd 2 1 " "Info: Using design file led_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 led_pio-europa " "Info: Found design unit 1: led_pio-europa" {  } { { "led_pio.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/led_pio.vhd" 37 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 led_pio " "Info: Found entity 1: led_pio" {  } { { "led_pio.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/led_pio.vhd" 21 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led_pio small_2C35:inst\|led_pio:the_led_pio " "Info: Elaborating entity \"led_pio\" for hierarchy \"small_2C35:inst\|led_pio:the_led_pio\"" {  } { { "small_2C35.vhd" "the_led_pio" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 1201 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onchip_ram_s1_arbitrator small_2C35:inst\|onchip_ram_s1_arbitrator:the_onchip_ram_s1 " "Info: Elaborating entity \"onchip_ram_s1_arbitrator\" for hierarchy \"small_2C35:inst\|onchip_ram_s1_arbitrator:the_onchip_ram_s1\"" {  } { { "small_2C35.vhd" "the_onchip_ram_s1" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 1214 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "onchip_ram.vhd 2 1 " "Info: Using design file onchip_ram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 onchip_ram-europa " "Info: Found design unit 1: onchip_ram-europa" {  } { { "onchip_ram.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/onchip_ram.vhd" 44 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 onchip_ram " "Info: Found entity 1: onchip_ram" {  } { { "onchip_ram.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/onchip_ram.vhd" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onchip_ram small_2C35:inst\|onchip_ram:the_onchip_ram " "Info: Elaborating entity \"onchip_ram\" for hierarchy \"small_2C35:inst\|onchip_ram:the_onchip_ram\"" {  } { { "small_2C35.vhd" "the_onchip_ram" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 1248 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram small_2C35:inst\|onchip_ram:the_onchip_ram\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"small_2C35:inst\|onchip_ram:the_onchip_ram\|altsyncram:the_altsyncram\"" {  } { { "onchip_ram.vhd" "the_altsyncram" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/onchip_ram.vhd" 132 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fh01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fh01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fh01 " "Info: Found entity 1: altsyncram_fh01" {  } { { "db/altsyncram_fh01.tdf" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/altsyncram_fh01.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fh01 small_2C35:inst\|onchip_ram:the_onchip_ram\|altsyncram:the_altsyncram\|altsyncram_fh01:auto_generated " "Info: Elaborating entity \"altsyncram_fh01\" for hierarchy \"small_2C35:inst\|onchip_ram:the_onchip_ram\|altsyncram:the_altsyncram\|altsyncram_fh01:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "small_2C35_reset_clk_domain_synch_module small_2C35:inst\|small_2C35_reset_clk_domain_synch_module:small_2C35_reset_clk_domain_synch " "Info: Elaborating entity \"small_2C35_reset_clk_domain_synch_module\" for hierarchy \"small_2C35:inst\|small_2C35_reset_clk_domain_synch_module:small_2C35_reset_clk_domain_synch\"" {  } { { "small_2C35.vhd" "small_2C35_reset_clk_domain_synch" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/small_2C35.vhd" 1262 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap-rtl " "Info: Found design unit 2: sld_signaltap-rtl" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 170 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 85 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd 14 7 " "Info: Found 14 design units, including 7 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_ela_control-rtl " "Info: Found design unit 1: sld_ela_control-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 118 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_ela_level_seq_mgr-rtl " "Info: Found design unit 2: sld_ela_level_seq_mgr-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 844 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_ela_state_machine-rtl " "Info: Found design unit 3: sld_ela_state_machine-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1022 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_ela_seg_state_machine-rtl " "Info: Found design unit 4: sld_ela_seg_state_machine-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1125 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 sld_ela_post_trigger_counter-rtl " "Info: Found design unit 5: sld_ela_post_trigger_counter-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1215 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 sld_ela_segment_mgr-rtl " "Info: Found design unit 6: sld_ela_segment_mgr-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1342 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 sld_ela_basic_multi_level_trigger-rtl " "Info: Found design unit 7: sld_ela_basic_multi_level_trigger-rtl" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1521 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_ela_control " "Info: Found entity 1: sld_ela_control" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 67 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_ela_level_seq_mgr " "Info: Found entity 2: sld_ela_level_seq_mgr" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 817 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 sld_ela_state_machine " "Info: Found entity 3: sld_ela_state_machine" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1000 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 sld_ela_seg_state_machine " "Info: Found entity 4: sld_ela_seg_state_machine" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1105 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 sld_ela_post_trigger_counter " "Info: Found entity 5: sld_ela_post_trigger_counter" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1195 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 sld_ela_segment_mgr " "Info: Found entity 6: sld_ela_segment_mgr" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1319 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 sld_ela_basic_multi_level_trigger " "Info: Found entity 7: sld_ela_basic_multi_level_trigger" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1487 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 37 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mbpmg-rtl " "Info: Found design unit 1: sld_mbpmg-rtl" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 65 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_sbpmg-rtl " "Info: Found design unit 2: sld_sbpmg-rtl" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 293 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mbpmg " "Info: Found entity 1: sld_mbpmg" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 44 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_sbpmg " "Info: Found entity 2: sld_sbpmg" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 272 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_a09.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_a09.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_a09 " "Info: Found entity 1: cntr_a09" {  } { { "db/cntr_a09.tdf" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/cntr_a09.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_2a9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_2a9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_2a9 " "Info: Found entity 1: cntr_2a9" {  } { { "db/cntr_2a9.tdf" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/db/cntr_2a9.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare " "Info: Found entity 1: lpm_compare" {  } { { "lpm_compare.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" 262 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/comptree.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/comptree.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 comptree " "Info: Found entity 1: comptree" {  } { { "comptree.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/comptree.tdf" 102 1 0 } }  } 0}  } {  } 0}