small.map.qmsg

38译码器的设计

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_11_is_x cpu_test_bench.vhd(190) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(190): object \"av_ld_data_aligned_unfiltered_11_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 190 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_12_is_x cpu_test_bench.vhd(191) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(191): object \"av_ld_data_aligned_unfiltered_12_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 191 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_13_is_x cpu_test_bench.vhd(192) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(192): object \"av_ld_data_aligned_unfiltered_13_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 192 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_14_is_x cpu_test_bench.vhd(193) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(193): object \"av_ld_data_aligned_unfiltered_14_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 193 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_15_is_x cpu_test_bench.vhd(194) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(194): object \"av_ld_data_aligned_unfiltered_15_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 194 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_16_is_x cpu_test_bench.vhd(195) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(195): object \"av_ld_data_aligned_unfiltered_16_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 195 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_17_is_x cpu_test_bench.vhd(196) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(196): object \"av_ld_data_aligned_unfiltered_17_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 196 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_18_is_x cpu_test_bench.vhd(197) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(197): object \"av_ld_data_aligned_unfiltered_18_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 197 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_19_is_x cpu_test_bench.vhd(198) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(198): object \"av_ld_data_aligned_unfiltered_19_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 198 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_1_is_x cpu_test_bench.vhd(199) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(199): object \"av_ld_data_aligned_unfiltered_1_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 199 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_20_is_x cpu_test_bench.vhd(200) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(200): object \"av_ld_data_aligned_unfiltered_20_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 200 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_21_is_x cpu_test_bench.vhd(201) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(201): object \"av_ld_data_aligned_unfiltered_21_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 201 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_22_is_x cpu_test_bench.vhd(202) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(202): object \"av_ld_data_aligned_unfiltered_22_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 202 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_23_is_x cpu_test_bench.vhd(203) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(203): object \"av_ld_data_aligned_unfiltered_23_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 203 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_24_is_x cpu_test_bench.vhd(204) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(204): object \"av_ld_data_aligned_unfiltered_24_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 204 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_25_is_x cpu_test_bench.vhd(205) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(205): object \"av_ld_data_aligned_unfiltered_25_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 205 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_26_is_x cpu_test_bench.vhd(206) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(206): object \"av_ld_data_aligned_unfiltered_26_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 206 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_27_is_x cpu_test_bench.vhd(207) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(207): object \"av_ld_data_aligned_unfiltered_27_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 207 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_28_is_x cpu_test_bench.vhd(208) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(208): object \"av_ld_data_aligned_unfiltered_28_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 208 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_29_is_x cpu_test_bench.vhd(209) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(209): object \"av_ld_data_aligned_unfiltered_29_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 209 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_2_is_x cpu_test_bench.vhd(210) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(210): object \"av_ld_data_aligned_unfiltered_2_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 210 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_30_is_x cpu_test_bench.vhd(211) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(211): object \"av_ld_data_aligned_unfiltered_30_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 211 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_31_is_x cpu_test_bench.vhd(212) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(212): object \"av_ld_data_aligned_unfiltered_31_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 212 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_3_is_x cpu_test_bench.vhd(213) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(213): object \"av_ld_data_aligned_unfiltered_3_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 213 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_4_is_x cpu_test_bench.vhd(214) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(214): object \"av_ld_data_aligned_unfiltered_4_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 214 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_5_is_x cpu_test_bench.vhd(215) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(215): object \"av_ld_data_aligned_unfiltered_5_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 215 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_6_is_x cpu_test_bench.vhd(216) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(216): object \"av_ld_data_aligned_unfiltered_6_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 216 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_7_is_x cpu_test_bench.vhd(217) " "Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(217): object \"av_ld_data_aligned_unfiltered_7_is_x\" declared but not used" {  } { { "cpu_test_bench.vhd" "" { Text "D:/GX_SOPC_Dev_Lab/EP2C35/EDA/BASE/lab7/cpu_test_bench.vhd" 217 0 0 } }  } 0}