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<TITLE>Analysis & Synthesis report for small</TITLE>
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<H1>Analysis & Synthesis report for small</H1>
<H3>Wed Apr 20 20:11:47 2005<BR>
Version 5.0 Build 146 04/13/2005 SJ Full Version</H3>
</CENTER>

<P><HR></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Table of Contents</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<OL>
<LI><A HREF="#1">Legal Notice</A></LI>
<LI><A HREF="#2">Analysis & Synthesis Summary</A></LI>
<LI><A HREF="#3">Analysis & Synthesis Settings</A></LI>
<LI><A HREF="#4">Analysis & Synthesis Source Files Read</A></LI>
<LI><A HREF="#5">Analysis & Synthesis Resource Usage Summary</A></LI>
<LI><A HREF="#6">Analysis & Synthesis Resource Utilization by Entity</A></LI>
<LI><A HREF="#7">Analysis & Synthesis RAM Summary</A></LI>
<LI><A HREF="#8">Registers Protected by SYN_PRESERVE, DONT_TOUCH</A></LI>
<LI><A HREF="#9">General Register Statistics</A></LI>
<LI><A HREF="#10">Inverted Register Statistics</A></LI>
<LI><A HREF="#11">Multiplexer Restructuring Statistics (Restructuring Performed)</A></LI>
<LI><A HREF="#12">Parameter Settings for User Entity Instance: small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf</A></LI>
<LI><A HREF="#13">Parameter Settings for User Entity Instance: small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram</A></LI>
<LI><A HREF="#14">Parameter Settings for User Entity Instance: small_2C35:inst|onchip_ram:the_onchip_ram|altsyncram:the_altsyncram</A></LI>
<LI><A HREF="#15">Analysis & Synthesis Equations</A></LI>
<LI><A HREF="#16">Analysis & Synthesis Messages</A></LI>
</OL>

<P><A NAME="1"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Legal Notice</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.
</PRE>

<P><A NAME="2"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle">
<TD ALIGN="LEFT">Analysis & Synthesis Status</TH>
<TD ALIGN="LEFT">Successful - Wed Apr 20 20:11:47 2005</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Quartus II Version</TD>
<TD ALIGN="LEFT">5.0 Build 146 04/13/2005 SJ Full Version</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Revision Name</TD>
<TD ALIGN="LEFT">small</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Top-level Entity Name</TD>
<TD ALIGN="LEFT">small</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Family</TD>
<TD ALIGN="LEFT">Cyclone II</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total combinational functions</TD>
<TD ALIGN="LEFT">555</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total registers</TD>
<TD ALIGN="LEFT">306</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total pins</TD>
<TD ALIGN="LEFT">10</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total virtual pins</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">17,408</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Embedded Multiplier 9-bit elements</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total PLLs</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
</TABLE>
<P><A NAME="3"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
<TH>Default Value</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device</TD>
<TD ALIGN="LEFT">EP2C35F672C6</TD>
<TD ALIGN="LEFT">&nbsp;</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Top-level entity name</TD>
<TD ALIGN="LEFT">small</TD>
<TD ALIGN="LEFT">small</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Family name</TD>
<TD ALIGN="LEFT">cycloneII</TD>
<TD ALIGN="LEFT">Stratix</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Use smart compilation</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Restructure Multiplexers</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Create Debugging Nodes for IP Cores</TD>
<TD ALIGN="LEFT">off</TD>
<TD ALIGN="LEFT">off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Preserve fewer node names</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Disable OpenCore Plus hardware evaluation</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Verilog Version</TD>
<TD ALIGN="LEFT">Verilog_2001</TD>
<TD ALIGN="LEFT">Verilog_2001</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">VHDL Version</TD>
<TD ALIGN="LEFT">VHDL93</TD>
<TD ALIGN="LEFT">VHDL93</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">State Machine Processing</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Extract Verilog State Machines</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Extract VHDL State Machines</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Add Pass-Through Logic to Inferred RAMs</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DSP Block Balancing</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum DSP Block Usage</TD>
<TD ALIGN="LEFT">-1</TD>
<TD ALIGN="LEFT">-1</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">NOT Gate Push-Back</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Power-Up Don't Care</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Remove Redundant Logic Cells</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Remove Duplicate Registers</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore CARRY Buffers</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore CASCADE Buffers</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore GLOBAL Buffers</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore ROW GLOBAL Buffers</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore LCELL Buffers</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore SOFT Buffers</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Limit AHDL Integers to 32 Bits</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimization Technique -- Cyclone II</TD>
<TD ALIGN="LEFT">Balanced</TD>
<TD ALIGN="LEFT">Balanced</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II</TD>
<TD ALIGN="LEFT">70</TD>
<TD ALIGN="LEFT">70</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Carry Chains</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Open-Drain Pins</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Remove Duplicate Logic</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform WYSIWYG Primitive Resynthesis</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform gate-level register retiming</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Allow register retiming to trade off Tsu/Tco with Fmax</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto ROM Replacement</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto RAM Replacement</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Shift Register Replacement</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Clock Enable Replacement</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Allows Synchronous Control Signal Usage in Normal Mode Logic Cells</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Resource Sharing</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Allow Any RAM Size For Recognition</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Allow Any ROM Size For Recognition</TD>
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