small_2c35.vhd

38译码器的设计

    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        cpu_data_master_read_data_valid_onchip_ram_s1_shift_register <= p1_cpu_data_master_read_data_valid_onchip_ram_s1_shift_register;
      end if;
    end if;

  end process;

  --local readdatavalid cpu_data_master_read_data_valid_onchip_ram_s1, which is an e_mux
  cpu_data_master_read_data_valid_onchip_ram_s1 <= cpu_data_master_read_data_valid_onchip_ram_s1_shift_register;
  --onchip_ram_s1_writedata mux, which is an e_mux
  onchip_ram_s1_writedata <= cpu_data_master_writedata;
  --mux onchip_ram_s1_clken, which is an e_mux
  onchip_ram_s1_clken <= std_logic'('1');
  internal_cpu_instruction_master_requests_onchip_ram_s1 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((cpu_instruction_master_read))))));
  --cpu/data_master granted onchip_ram/s1 last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_cpu_data_master_granted_slave_onchip_ram_s1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_cpu_data_master_granted_slave_onchip_ram_s1 <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(cpu_data_master_saved_grant_onchip_ram_s1) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((onchip_ram_s1_arbitration_holdoff_internal OR NOT internal_cpu_data_master_requests_onchip_ram_s1))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_cpu_data_master_granted_slave_onchip_ram_s1))))));
      end if;
    end if;

  end process;

  --cpu_data_master_continuerequest continued request, which is an e_mux
  cpu_data_master_continuerequest <= last_cycle_cpu_data_master_granted_slave_onchip_ram_s1 AND internal_cpu_data_master_requests_onchip_ram_s1;
  internal_cpu_instruction_master_qualified_request_onchip_ram_s1 <= internal_cpu_instruction_master_requests_onchip_ram_s1 AND NOT ((((cpu_instruction_master_read AND (cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register))) OR cpu_data_master_arbiterlock));
  --cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register_in <= ((internal_cpu_instruction_master_granted_onchip_ram_s1 AND cpu_instruction_master_read) AND NOT onchip_ram_s1_waits_for_read) AND NOT (cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register);
  --shift register p1 cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  p1_cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register <= Vector_To_Std_Logic(Std_Logic_Vector'(A_ToStdLogicVector(cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register) & A_ToStdLogicVector(cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register_in)));
  --cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register <= p1_cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register;
      end if;
    end if;

  end process;

  --local readdatavalid cpu_instruction_master_read_data_valid_onchip_ram_s1, which is an e_mux
  cpu_instruction_master_read_data_valid_onchip_ram_s1 <= cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register;
  --allow new arb cycle for onchip_ram/s1, which is an e_assign
  onchip_ram_s1_allow_new_arb_cycle <= NOT cpu_data_master_arbiterlock AND NOT cpu_instruction_master_arbiterlock;
  --cpu/instruction_master assignment into master qualified-requests vector for onchip_ram/s1, which is an e_assign
  onchip_ram_s1_master_qreq_vector(0) <= internal_cpu_instruction_master_qualified_request_onchip_ram_s1;
  --cpu/instruction_master grant onchip_ram/s1, which is an e_assign
  internal_cpu_instruction_master_granted_onchip_ram_s1 <= onchip_ram_s1_grant_vector(0);
  --cpu/instruction_master saved-grant onchip_ram/s1, which is an e_assign
  cpu_instruction_master_saved_grant_onchip_ram_s1 <= onchip_ram_s1_arb_winner(0) AND internal_cpu_instruction_master_requests_onchip_ram_s1;
  --cpu/data_master assignment into master qualified-requests vector for onchip_ram/s1, which is an e_assign
  onchip_ram_s1_master_qreq_vector(1) <= internal_cpu_data_master_qualified_request_onchip_ram_s1;
  --cpu/data_master grant onchip_ram/s1, which is an e_assign
  internal_cpu_data_master_granted_onchip_ram_s1 <= onchip_ram_s1_grant_vector(1);
  --cpu/data_master saved-grant onchip_ram/s1, which is an e_assign
  cpu_data_master_saved_grant_onchip_ram_s1 <= onchip_ram_s1_arb_winner(1) AND internal_cpu_data_master_requests_onchip_ram_s1;
  --onchip_ram/s1 chosen-master double-vector, which is an e_assign
  onchip_ram_s1_chosen_master_double_vector <= A_EXT (((std_logic_vector'("0") & ((onchip_ram_s1_master_qreq_vector & onchip_ram_s1_master_qreq_vector))) AND (((std_logic_vector'("0") & (Std_Logic_Vector'(NOT onchip_ram_s1_master_qreq_vector & NOT onchip_ram_s1_master_qreq_vector))) + (std_logic_vector'("000") & (onchip_ram_s1_arb_addend))))), 4);
  --stable onehot encoding of arb winner
  onchip_ram_s1_arb_winner <= A_WE_StdLogicVector((std_logic'(((onchip_ram_s1_allow_new_arb_cycle AND or_reduce(onchip_ram_s1_grant_vector)))) = '1'), onchip_ram_s1_grant_vector, onchip_ram_s1_saved_chosen_master_vector);
  --saved onchip_ram_s1_grant_vector, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      onchip_ram_s1_saved_chosen_master_vector <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(onchip_ram_s1_allow_new_arb_cycle) = '1' then 
        onchip_ram_s1_saved_chosen_master_vector <= A_WE_StdLogicVector((std_logic'(or_reduce(onchip_ram_s1_grant_vector)) = '1'), onchip_ram_s1_grant_vector, onchip_ram_s1_saved_chosen_master_vector);
      end if;
    end if;

  end process;

  --onehot encoding of chosen master
  onchip_ram_s1_grant_vector <= Std_Logic_Vector'(A_ToStdLogicVector(((onchip_ram_s1_chosen_master_double_vector(1) OR onchip_ram_s1_chosen_master_double_vector(3)))) & A_ToStdLogicVector(((onchip_ram_s1_chosen_master_double_vector(0) OR onchip_ram_s1_chosen_master_double_vector(2)))));
  --onchip_ram/s1 chosen master rotated left, which is an e_assign
  onchip_ram_s1_chosen_master_rot_left <= A_EXT (A_WE_StdLogicVector((((A_SLL(onchip_ram_s1_arb_winner,std_logic_vector'("00000000000000000000000000000001")))) /= std_logic_vector'("00")), (std_logic_vector'("000000000000000000000000000000") & ((A_SLL(onchip_ram_s1_arb_winner,std_logic_vector'("00000000000000000000000000000001"))))), std_logic_vector'("00000000000000000000000000000001")), 2);
  --onchip_ram/s1's addend for next-master-grant
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      onchip_ram_s1_arb_addend <= std_logic_vector'("01");
    elsif clk'event and clk = '1' then
      if std_logic'(or_reduce(onchip_ram_s1_grant_vector)) = '1' then 
        onchip_ram_s1_arb_addend <= A_WE_StdLogicVector((std_logic'(onchip_ram_s1_end_xfer) = '1'), onchip_ram_s1_chosen_master_rot_left, onchip_ram_s1_grant_vector);
      end if;
    end if;

  end process;

  onchip_ram_s1_chipselect <= internal_cpu_data_master_granted_onchip_ram_s1 OR internal_cpu_instruction_master_granted_onchip_ram_s1;
  --onchip_ram_s1_firsttransfer first transaction, which is an e_assign
  onchip_ram_s1_firsttransfer <= NOT ((onchip_ram_s1_slavearbiterlockenable AND onchip_ram_s1_any_continuerequest));
  --onchip_ram_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  onchip_ram_s1_beginbursttransfer_internal <= onchip_ram_s1_begins_xfer AND onchip_ram_s1_firsttransfer;
  --onchip_ram_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  onchip_ram_s1_arbitration_holdoff_internal <= onchip_ram_s1_begins_xfer AND onchip_ram_s1_firsttransfer;
  --onchip_ram_s1_write assignment, which is an e_mux
  onchip_ram_s1_write <= internal_cpu_data_master_granted_onchip_ram_s1 AND cpu_data_master_write;
  --onchip_ram_s1_address mux, which is an e_mux
  onchip_ram_s1_address <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_cpu_data_master_granted_onchip_ram_s1)) = '1'), (A_SRL(cpu_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010"))), (std_logic_vector'("0000") & ((A_SRL(cpu_instruction_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")))))), 9);
  --d1_onchip_ram_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_onchip_ram_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_onchip_ram_s1_end_xfer <= onchip_ram_s1_end_xfer;
      end if;
    end if;

  end process;

  --onchip_ram_s1_waits_for_read in a cycle, which is an e_mux
  onchip_ram_s1_waits_for_read <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(onchip_ram_s1_in_a_read_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --onchip_ram_s1_in_a_read_cycle assignment, which is an e_assign
  onchip_ram_s1_in_a_read_cycle <= ((internal_cpu_data_master_granted_onchip_ram_s1 AND cpu_data_master_read)) OR ((internal_cpu_instruction_master_granted_onchip_ram_s1 AND cpu_instruction_master_read));
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= onchip_ram_s1_in_a_read_cycle;
  --onchip_ram_s1_waits_for_write in a cycle, which is an e_mux
  onchip_ram_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(onchip_ram_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --onchip_ram_s1_in_a_write_cycle assignment, which is an e_assign
  onchip_ram_s1_in_a_write_cycle <= internal_cpu_data_master_granted_onchip_ram_s1 AND cpu_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= onchip_ram_s1_in_a_write_cycle;
  wait_for_onchip_ram_s1_counter <= std_logic'('0');
  --onchip_ram_s1_byteenable byte enable port mux, which is an e_mux
  onchip_ram_s1_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_cpu_data_master_granted_onchip_ram_s1)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (cpu_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
  --vhdl renameroo for output signals
  cpu_data_master_granted_onchip_ram_s1 <= internal_cpu_data_master_granted_onchip_ram_s1;
  --vhdl renameroo for output signals
  cpu_data_master_qualified_request_onchip_ram_s1 <= internal_cpu_data_master_qualified_request_onchip_ram_s1;
  --vhdl renameroo for output signals
  cpu_data_master_requests_onchip_ram_s1 <= internal_cpu_data_master_requests_onchip_ram_s1;
  --vhdl renameroo for output signals
  cpu_instruction_master_granted_onchip_ram_s1 <= internal_cpu_instruction_master_granted_onchip_ram_s1;
  --vhdl renameroo for output signals
  cpu_instruction_master_qualified_request_onchip_ram_s1 <= internal_cpu_instruction_master_qualified_request_onchip_ram_s1;
  --vhdl renameroo for output signals
  cpu_instruction_master_requests_onchip_ram_s1 <= internal_cpu_instruction_master_requests_onchip_ram_s1;
--synthesis translate_off
    --grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line2 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_cpu_data_master_granted_onchip_ram_s1))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_cpu_instruction_master_granted_onchip_ram_s1))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line2, now);
          write(write_line2, string'(": "));
          write(write_line2, string'("> 1 of grant signals are active simultaneously"));
          write(output, write_line2.all);
          deallocate (write_line2);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

    --saved_grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line3 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(cpu_data_master_saved_grant_onchip_ram_s1))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(cpu_instruction_master_saved_grant_onchip_ram_s1))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line3, now);
          write(write_line3, string'(": "));
          write(write_line3, string'("> 1 of saved_grant signals are active simultaneously"));
          write(output, write_line3.all);
          deallocate (write_line3);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

--synthesis translate_on

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity small_2C35_reset_clk_domain_synch_module is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal data_in : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs: