small_2c35.vhd

38译码器的设计

  led_pio_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(led_pio_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --led_pio_s1_in_a_write_cycle assignment, which is an e_assign
  led_pio_s1_in_a_write_cycle <= internal_cpu_data_master_granted_led_pio_s1 AND cpu_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= led_pio_s1_in_a_write_cycle;
  wait_for_led_pio_s1_counter <= std_logic'('0');
  --led_pio_s1_pretend_byte_enable byte enable port mux, which is an e_mux
  led_pio_s1_pretend_byte_enable <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((internal_cpu_data_master_granted_led_pio_s1)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (cpu_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))));
  --vhdl renameroo for output signals
  cpu_data_master_granted_led_pio_s1 <= internal_cpu_data_master_granted_led_pio_s1;
  --vhdl renameroo for output signals
  cpu_data_master_qualified_request_led_pio_s1 <= internal_cpu_data_master_qualified_request_led_pio_s1;
  --vhdl renameroo for output signals
  cpu_data_master_requests_led_pio_s1 <= internal_cpu_data_master_requests_led_pio_s1;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity onchip_ram_s1_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal cpu_data_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
                 signal cpu_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_data_master_read : IN STD_LOGIC;
                 signal cpu_data_master_waitrequest : IN STD_LOGIC;
                 signal cpu_data_master_write : IN STD_LOGIC;
                 signal cpu_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
                 signal cpu_instruction_master_read : IN STD_LOGIC;
                 signal onchip_ram_s1_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal cpu_data_master_granted_onchip_ram_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_qualified_request_onchip_ram_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_read_data_valid_onchip_ram_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_requests_onchip_ram_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_granted_onchip_ram_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_onchip_ram_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_read_data_valid_onchip_ram_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_requests_onchip_ram_s1 : OUT STD_LOGIC;
                 signal d1_onchip_ram_s1_end_xfer : OUT STD_LOGIC;
                 signal onchip_ram_s1_address : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
                 signal onchip_ram_s1_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal onchip_ram_s1_chipselect : OUT STD_LOGIC;
                 signal onchip_ram_s1_clken : OUT STD_LOGIC;
                 signal onchip_ram_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal onchip_ram_s1_write : OUT STD_LOGIC;
                 signal onchip_ram_s1_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal registered_cpu_data_master_read_data_valid_onchip_ram_s1 : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of onchip_ram_s1_arbitrator : entity is FALSE;
end entity onchip_ram_s1_arbitrator;


architecture europa of onchip_ram_s1_arbitrator is
                signal cpu_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_data_master_continuerequest :  STD_LOGIC;
                signal cpu_data_master_read_data_valid_onchip_ram_s1_shift_register :  STD_LOGIC;
                signal cpu_data_master_read_data_valid_onchip_ram_s1_shift_register_in :  STD_LOGIC;
                signal cpu_data_master_saved_grant_onchip_ram_s1 :  STD_LOGIC;
                signal cpu_instruction_master_arbiterlock :  STD_LOGIC;
                signal cpu_instruction_master_continuerequest :  STD_LOGIC;
                signal cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register :  STD_LOGIC;
                signal cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register_in :  STD_LOGIC;
                signal cpu_instruction_master_saved_grant_onchip_ram_s1 :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_cpu_data_master_granted_onchip_ram_s1 :  STD_LOGIC;
                signal internal_cpu_data_master_qualified_request_onchip_ram_s1 :  STD_LOGIC;
                signal internal_cpu_data_master_requests_onchip_ram_s1 :  STD_LOGIC;
                signal internal_cpu_instruction_master_granted_onchip_ram_s1 :  STD_LOGIC;
                signal internal_cpu_instruction_master_qualified_request_onchip_ram_s1 :  STD_LOGIC;
                signal internal_cpu_instruction_master_requests_onchip_ram_s1 :  STD_LOGIC;
                signal last_cycle_cpu_data_master_granted_slave_onchip_ram_s1 :  STD_LOGIC;
                signal last_cycle_cpu_instruction_master_granted_slave_onchip_ram_s1 :  STD_LOGIC;
                signal onchip_ram_s1_allgrants :  STD_LOGIC;
                signal onchip_ram_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal onchip_ram_s1_any_continuerequest :  STD_LOGIC;
                signal onchip_ram_s1_arb_addend :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_ram_s1_arb_counter_enable :  STD_LOGIC;
                signal onchip_ram_s1_arb_share_counter :  STD_LOGIC;
                signal onchip_ram_s1_arb_share_counter_next_value :  STD_LOGIC;
                signal onchip_ram_s1_arb_share_set_values :  STD_LOGIC;
                signal onchip_ram_s1_arb_winner :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_ram_s1_arbitration_holdoff_internal :  STD_LOGIC;
                signal onchip_ram_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal onchip_ram_s1_begins_xfer :  STD_LOGIC;
                signal onchip_ram_s1_chosen_master_double_vector :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal onchip_ram_s1_chosen_master_rot_left :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_ram_s1_end_xfer :  STD_LOGIC;
                signal onchip_ram_s1_firsttransfer :  STD_LOGIC;
                signal onchip_ram_s1_grant_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_ram_s1_in_a_read_cycle :  STD_LOGIC;
                signal onchip_ram_s1_in_a_write_cycle :  STD_LOGIC;
                signal onchip_ram_s1_master_qreq_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_ram_s1_saved_chosen_master_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_ram_s1_slavearbiterlockenable :  STD_LOGIC;
                signal onchip_ram_s1_waits_for_read :  STD_LOGIC;
                signal onchip_ram_s1_waits_for_write :  STD_LOGIC;
                signal p1_cpu_data_master_read_data_valid_onchip_ram_s1_shift_register :  STD_LOGIC;
                signal p1_cpu_instruction_master_read_data_valid_onchip_ram_s1_shift_register :  STD_LOGIC;
                signal wait_for_onchip_ram_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT onchip_ram_s1_end_xfer;
      end if;
    end if;

  end process;

  onchip_ram_s1_begins_xfer <= NOT d1_reasons_to_wait AND ((internal_cpu_data_master_qualified_request_onchip_ram_s1 OR internal_cpu_instruction_master_qualified_request_onchip_ram_s1));
  internal_cpu_data_master_requests_onchip_ram_s1 <= to_std_logic(((Std_Logic_Vector'(cpu_data_master_address_to_slave(14 DOWNTO 11) & std_logic_vector'("00000000000")) = std_logic_vector'("000000000000000")))) AND ((cpu_data_master_read OR cpu_data_master_write));
  --assign onchip_ram_s1_readdata_from_sa = onchip_ram_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  onchip_ram_s1_readdata_from_sa <= onchip_ram_s1_readdata;
  --registered rdv signal_name registered_cpu_data_master_read_data_valid_onchip_ram_s1 assignment, which is an e_assign
  registered_cpu_data_master_read_data_valid_onchip_ram_s1 <= cpu_data_master_read_data_valid_onchip_ram_s1_shift_register_in;
  --onchip_ram_s1_arb_share_counter set values, which is an e_mux
  onchip_ram_s1_arb_share_set_values <= std_logic'('1');
  --onchip_ram_s1_arb_share_counter_next_value assignment, which is an e_assign
  onchip_ram_s1_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(onchip_ram_s1_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(onchip_ram_s1_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(onchip_ram_s1_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(onchip_ram_s1_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --onchip_ram_s1_allgrants all slave grants, which is an e_mux
  onchip_ram_s1_allgrants <= ((or_reduce(onchip_ram_s1_grant_vector) OR or_reduce(onchip_ram_s1_grant_vector)) OR or_reduce(onchip_ram_s1_grant_vector)) OR or_reduce(onchip_ram_s1_grant_vector);
  --onchip_ram_s1_end_xfer assignment, which is an e_assign
  onchip_ram_s1_end_xfer <= NOT ((onchip_ram_s1_waits_for_read OR onchip_ram_s1_waits_for_write));
  --onchip_ram_s1_arb_share_counter arbitration counter enable, which is an e_assign
  onchip_ram_s1_arb_counter_enable <= onchip_ram_s1_end_xfer AND onchip_ram_s1_allgrants;
  --onchip_ram_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      onchip_ram_s1_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(onchip_ram_s1_arb_counter_enable) = '1' then 
        onchip_ram_s1_arb_share_counter <= onchip_ram_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --onchip_ram_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      onchip_ram_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((or_reduce(onchip_ram_s1_master_qreq_vector) AND onchip_ram_s1_end_xfer)) = '1' then 
        onchip_ram_s1_slavearbiterlockenable <= onchip_ram_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu/data_master onchip_ram/s1 arbiterlock, which is an e_assign
  cpu_data_master_arbiterlock <= onchip_ram_s1_slavearbiterlockenable AND cpu_data_master_continuerequest;
  --cpu/instruction_master onchip_ram/s1 arbiterlock, which is an e_assign
  cpu_instruction_master_arbiterlock <= onchip_ram_s1_slavearbiterlockenable AND cpu_instruction_master_continuerequest;
  --cpu/instruction_master granted onchip_ram/s1 last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_cpu_instruction_master_granted_slave_onchip_ram_s1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_cpu_instruction_master_granted_slave_onchip_ram_s1 <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(cpu_instruction_master_saved_grant_onchip_ram_s1) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((onchip_ram_s1_arbitration_holdoff_internal OR NOT internal_cpu_instruction_master_requests_onchip_ram_s1))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_cpu_instruction_master_granted_slave_onchip_ram_s1))))));
      end if;
    end if;

  end process;

  --cpu_instruction_master_continuerequest continued request, which is an e_mux
  cpu_instruction_master_continuerequest <= last_cycle_cpu_instruction_master_granted_slave_onchip_ram_s1 AND internal_cpu_instruction_master_requests_onchip_ram_s1;
  --onchip_ram_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  onchip_ram_s1_any_continuerequest <= cpu_instruction_master_continuerequest OR cpu_data_master_continuerequest;
  internal_cpu_data_master_qualified_request_onchip_ram_s1 <= internal_cpu_data_master_requests_onchip_ram_s1 AND NOT (((((cpu_data_master_read AND (cpu_data_master_read_data_valid_onchip_ram_s1_shift_register))) OR (((NOT cpu_data_master_waitrequest) AND cpu_data_master_write))) OR cpu_instruction_master_arbiterlock));
  --cpu_data_master_read_data_valid_onchip_ram_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  cpu_data_master_read_data_valid_onchip_ram_s1_shift_register_in <= ((internal_cpu_data_master_granted_onchip_ram_s1 AND cpu_data_master_read) AND NOT onchip_ram_s1_waits_for_read) AND NOT (cpu_data_master_read_data_valid_onchip_ram_s1_shift_register);
  --shift register p1 cpu_data_master_read_data_valid_onchip_ram_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  p1_cpu_data_master_read_data_valid_onchip_ram_s1_shift_register <= Vector_To_Std_Logic(Std_Logic_Vector'(A_ToStdLogicVector(cpu_data_master_read_data_valid_onchip_ram_s1_shift_register) & A_ToStdLogicVector(cpu_data_master_read_data_valid_onchip_ram_s1_shift_register_in)));
  --cpu_data_master_read_data_valid_onchip_ram_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      cpu_data_master_read_data_valid_onchip_ram_s1_shift_register <= std_logic'('0');