small.tan.rpt

38译码器的设计

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------+--------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack                                    ; Required Time ; Actual Time                      ; From                                               ; To                                                                       ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------+--------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A                                      ; None          ; 7.236 ns                         ; CLR                                                ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[3]                     ;                              ; osc_clk[0]                   ; 0            ;
; Worst-case tco                              ; N/A                                      ; None          ; 16.871 ns                        ; DFFLOP:inst3|Q~55                                  ; Q                                                                        ; osc_clk[0]                   ;                              ; 0            ;
; Worst-case tpd                              ; N/A                                      ; None          ; 16.850 ns                        ; CLR                                                ; Q                                                                        ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A                                      ; None          ; 1.802 ns                         ; altera_internal_jtag~TMSUTAP                       ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'osc_clk[0]'                   ; N/A                                      ; None          ; 125.93 MHz ( period = 7.941 ns ) ; small_2C35:inst|cpu:the_cpu|R_logic_op[1]          ; small_2C35:inst|cpu:the_cpu|W_cmp_result                                 ; osc_clk[0]                   ; osc_clk[0]                   ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A                                      ; None          ; 130.68 MHz ( period = 7.652 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] ; sld_hub:sld_hub_inst|hub_tdo                                             ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Hold: 'osc_clk[0]'                    ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; TFFLOP:inst4|QT                                    ; TFFLOP:inst4|QT                                                          ; osc_clk[0]                   ; osc_clk[0]                   ; 1            ;
; Total number of failed paths                ;                                          ;               ;                                  ;                                                    ;                                                                          ;                              ;                              ; 1            ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------+--------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C8       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+