adder8.fit.summary

8位加法器的实现

Fitter Status : Successful - Thu May 08 16:35:13 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : adder8
Top-level Entity Name : adder8
Family : Stratix II
Device : EP2S15F672C3
Timing Models : Final
Logic utilization : < 1 %
    Combinational ALUTs : 12 / 12,480 ( < 1 % )
    Dedicated logic registers : 0 / 12,480 ( 0 % )
Total registers : 0
Total pins : 25 / 367 ( 7 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )