code.syr

16位cpu设计VHDL源码

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: code.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : code.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : code
Output Format                      : NGC
Target Device                      : xcv200-4-pq240

---- Source Options
Top Module Name                    : code
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : code.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/资料/计算机设计与实践/MyCPU16/code.vhdl in Library work.
Architecture behavioral of Entity code is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <code> (Architecture <behavioral>).
WARNING:Xst:766 - E:/资料/计算机设计与实践/MyCPU16/code.vhdl line 29: Generating a Black Box for component <bufgp>.
WARNING:Xst:819 - E:/资料/计算机设计与实践/MyCPU16/code.vhdl line 30: The following signals are missing in the process sensitivity list:
   PCnew, PC, IRnew.
Entity <code> analyzed. Unit <code> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <code>.
    Related source file is E:/资料/计算机设计与实践/MyCPU16/code.vhdl.
WARNING:Xst:646 - Signal <clkgp> is assigned but never used.
WARNING:Xst:737 - Found 16-bit latch for signal <IR>.
WARNING:Xst:737 - Found 16-bit latch for signal <PCout>.
    Found 16-bit register for signal <IRout>.
    Found 16-bit up counter for signal <PC>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred  16 D-type flip-flop(s).
	inferred  16 Multiplexer(s).
Unit <code> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 16-bit up counter                 : 1
# Registers                        : 1
 16-bit register                   : 1
# Latches                          : 2
 16-bit latch                      : 2
# Multiplexers                     : 1
 16-bit 2-to-1 multiplexer         : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <code> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block code, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : code.ngr
Top Level Output File Name         : code
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 70

Macro Statistics :
# Registers                        : 1
#      16-bit register             : 1
# Multiplexers                     : 2
#      2-to-1 multiplexer          : 2
# Adders/Subtractors               : 1
#      16-bit adder                : 1

Cell Usage :
# BELS                             : 117
#      GND                         : 1
#      LUT1                        : 3
#      LUT1_L                      : 16
#      LUT2                        : 16
#      LUT3                        : 35
#      LUT3_L                      : 15
#      MUXCY                       : 15
#      VCC                         : 1
#      XORCY                       : 15
# FlipFlops/Latches                : 64
#      FDCPE                       : 16
#      FDE                         : 16
#      LDCE_1                      : 16
#      LDE                         : 16
# Clock Buffers                    : 4
#      BUFGP                       : 4
# IO Buffers                       : 66
#      IBUF                        : 33
#      OBUF                        : 33
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4