📄 memory.par
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Release 6.2i Par G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.song:: Sun Nov 11 22:54:39 2007C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 memory_map.ncd
memory.ncd memory.pcf Constraints file: memory.pcfLoading device database for application Par from file "memory_map.ncd". "memory" is an NCD, version 2.38, device xcv200, package pq240, speed -4Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.Device speed data version: FINAL 1.123 2003-12-13.Device utilization summary: Number of External IOBs 21 out of 166 12% Number of LOCed External IOBs 0 out of 21 0% Number of SLICEs 1 out of 2352 1%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:9896ab) REAL time: 0 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8.Phase 5.8 (Checksum:98af1b) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file memory.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 15 unrouted; REAL time: 0 secs Phase 2: 15 unrouted; REAL time: 0 secs Phase 3: 0 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. The Delay Summary Report The SCORE FOR THIS DESIGN is: 111The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: 0.912 The MAXIMUM PIN DELAY IS: 1.367 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 0.976 Listing Pin Delays by value: (nsec) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00 --------- --------- --------- --------- --------- --------- 10 5 0 0 0 0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 2 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 53 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file memory.ncd.PAR done.
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