visit_memory.bld

16位cpu设计VHDL源码

Release 6.2i - ngdbuild G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -intstyle ise -dd e:\资料\计算机设计与实践\mycpu16/_ngo
-i -p xcv200-pq240-4 visit_memory.ngc visit_memory.ngd 

Reading NGO file "E:/资料/计算机设计与实践/MyCPU16/visit_memory.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'PCload_BUFGP' has non-clock connections. These
   problematic connections include:
     pin I0 on block nWR1 with type LUT2,
     pin I0 on block nMREQ1 with type LUT3,
     pin I0 on block nBHE1 with type LUT1,
     pin I0 on block nRD1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<15>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<0>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<1>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<2>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<3>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<4>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<5>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<6>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<7>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<8>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<9>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<10>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<11>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<12>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<13>1 with type LUT3,
     pin I0 on block Mmux__n0007_Result<14>1 with type LUT3
WARNING:NgdBuild:478 - clock net 'u1/O' drives no clock pins

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   2

Total memory usage is 39216 kilobytes

Writing NGD file "visit_memory.ngd" ...

Writing NGDBUILD log file "visit_memory.bld"...