code.bld

16位cpu设计VHDL源码

Release 6.2i - ngdbuild G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -intstyle ise -dd e:\资料\计算机设计与实践\mycpu16/_ngo
-i -p xcv200-pq240-4 code.ngc code.ngd 

Reading NGO file "E:/资料/计算机设计与实践/MyCPU16/code.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'PCupdate_BUFGP' has non-clock connections.
   These problematic connections include:
     pin I2 on block _n00071 with type LUT3,
     pin I2 on block PCload1 with type LUT3,
     pin I0 on block PCout_0__n00011 with type LUT1,
     pin I0 on block PC_0__n00011 with type LUT2,
     pin I0 on block PC_15__n00001 with type LUT3,
     pin I0 on block PC_14__n00001 with type LUT3,
     pin I0 on block PC_0__n00001 with type LUT3,
     pin I0 on block PC_1__n00001 with type LUT3,
     pin I0 on block PC_2__n00001 with type LUT3,
     pin I0 on block PC_3__n00001 with type LUT3,
     pin I0 on block PC_4__n00001 with type LUT3,
     pin I0 on block PC_5__n00001 with type LUT3,
     pin I0 on block PC_6__n00001 with type LUT3,
     pin I0 on block PC_7__n00001 with type LUT3,
     pin I0 on block PC_8__n00001 with type LUT3,
     pin I0 on block PC_9__n00001 with type LUT3,
     pin I0 on block PC_10__n00001 with type LUT3,
     pin I0 on block PC_11__n00001 with type LUT3,
     pin I0 on block PC_12__n00001 with type LUT3,
     pin I0 on block PC_13__n00001 with type LUT3
WARNING:NgdBuild:477 - clock net 'RST_BUFGP' has non-clock connections. These
   problematic connections include:
     pin I1 on block _n00071 with type LUT3,
     pin I1 on block PCload1 with type LUT3,
     pin I0 on block IR_0__n00011 with type LUT1,
     pin I2 on block PC_15__n00001 with type LUT3,
     pin I2 on block PC_14__n00001 with type LUT3,
     pin I2 on block PC_0__n00001 with type LUT3,
     pin I2 on block PC_1__n00001 with type LUT3,
     pin I2 on block PC_2__n00001 with type LUT3,
     pin I2 on block PC_3__n00001 with type LUT3,
     pin I2 on block PC_4__n00001 with type LUT3,
     pin I2 on block PC_5__n00001 with type LUT3,
     pin I2 on block PC_6__n00001 with type LUT3,
     pin I2 on block PC_7__n00001 with type LUT3,
     pin I2 on block PC_8__n00001 with type LUT3,
     pin I2 on block PC_9__n00001 with type LUT3,
     pin I2 on block PC_10__n00001 with type LUT3,
     pin I2 on block PC_11__n00001 with type LUT3,
     pin I2 on block PC_12__n00001 with type LUT3,
     pin I2 on block PC_13__n00001 with type LUT3
WARNING:NgdBuild:478 - clock net 'u1/O' drives no clock pins

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   3

Total memory usage is 39216 kilobytes

Writing NGD file "code.ngd" ...

Writing NGDBUILD log file "code.bld"...