code.par

16位cpu设计VHDL源码

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

song::  Sun Nov 11 22:54:11 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 code_map.ncd code.ncd
code.pcf 


Constraints file: code.pcf

Loading device database for application Par from file "code_map.ncd".
   "code" is an NCD, version 2.38, device xcv200, package pq240, speed -4
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  FINAL 1.123 2003-12-13.


Device utilization summary:

   Number of External GCLKIOBs         3 out of 4      75%
   Number of External IOBs            66 out of 166    39%
      Number of LOCed External IOBs    0 out of 66      0%

   Number of SLICEs                   41 out of 2352    1%

   Number of GCLKs                     3 out of 4      75%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989891) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9bb3f5) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file code.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 403 unrouted;       REAL time: 0 secs 

Phase 2: 347 unrouted;       REAL time: 0 secs 

Phase 3: 61 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|    PCupdate_BUFGP          |  Global  |   74   |  0.054     |  0.650      |
+----------------------------+----------+--------+------------+-------------+
|         RST_BUFGP          |  Global  |   42   |  0.010     |  0.585      |
+----------------------------+----------+--------+------------+-------------+
|          T1_BUFGP          |  Global  |   32   |  0.086     |  0.611      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 393


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.867
   The MAXIMUM PIN DELAY IS:                               9.453
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   5.318

   Listing Pin Delays by value: (nsec)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 10.00  d >= 10.00
   ---------   ---------   ---------   ---------   ---------   ---------
         193          92          81          19          18           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file code.ncd.


PAR done.