vga_colour_bar.fit.summary

来自「用verilog hdl实现的VGA显示彩条信号」· SUMMARY 代码 · 共 18 行

Fitter Status : Successful - Wed May 14 10:44:05 2008
Quartus II Version : 7.1 Build 178 06/25/2007 SP 1 SJ Full Version
Revision Name : vga_colour_bar
Top-level Entity Name : vga_colour_bar
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : < 1 %
    Combinational ALUTs : 49 / 12,480 ( < 1 % )
    Dedicated logic registers : 26 / 12,480 ( < 1 % )
Total registers : 26
Total pins : 61 / 343 ( 18 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )