prev_cmp_vga_colour_bar.tan.qmsg

用verilog hdl实现的VGA显示彩条信号

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "enmode 6 " "Warning: Circuit may not operate. Detected 6 non-operational path(s) clocked by clock \"enmode\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "mode\[0\]~reg0 B\[0\]\$latch enmode 2.297 ns " "Info: Found hold time violation between source  pin or register \"mode\[0\]~reg0\" and destination pin or register \"B\[0\]\$latch\" for clock \"enmode\" (Hold time is 2.297 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.351 ns + Largest " "Info: + Largest clock skew is 3.351 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "enmode destination 5.876 ns + Longest register " "Info: + Longest clock path from clock \"enmode\" to destination register is 5.876 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.799 ns) 0.799 ns enmode 1 CLK PIN_C13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_C13; Fanout = 2; CLK Node = 'enmode'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { enmode } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.108 ns) + CELL(0.712 ns) 2.619 ns mode\[1\]~reg0 2 REG LCFF_X18_Y19_N13 7 " "Info: 2: + IC(1.108 ns) + CELL(0.712 ns) = 2.619 ns; Loc. = LCFF_X18_Y19_N13; Fanout = 7; REG Node = 'mode\[1\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.820 ns" { enmode mode[1]~reg0 } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 87 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.233 ns) + CELL(0.225 ns) 3.077 ns Mux6~13 3 COMB LCCOMB_X18_Y19_N18 1 " "Info: 3: + IC(0.233 ns) + CELL(0.225 ns) = 3.077 ns; Loc. = LCCOMB_X18_Y19_N18; Fanout = 1; COMB Node = 'Mux6~13'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { mode[1]~reg0 Mux6~13 } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.000 ns) 4.777 ns Mux6~13clkctrl 4 COMB CLKCTRL_G13 3 " "Info: 4: + IC(1.700 ns) + CELL(0.000 ns) = 4.777 ns; Loc. = CLKCTRL_G13; Fanout = 3; COMB Node = 'Mux6~13clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { Mux6~13 Mux6~13clkctrl } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.225 ns) 5.876 ns B\[0\]\$latch 5 REG LCCOMB_X18_Y19_N4 8 " "Info: 5: + IC(0.874 ns) + CELL(0.225 ns) = 5.876 ns; Loc. = LCCOMB_X18_Y19_N4; Fanout = 8; REG Node = 'B\[0\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.099 ns" { Mux6~13clkctrl B[0]$latch } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.961 ns ( 33.37 % ) " "Info: Total cell delay = 1.961 ns ( 33.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.915 ns ( 66.63 % ) " "Info: Total interconnect delay = 3.915 ns ( 66.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.876 ns" { enmode mode[1]~reg0 Mux6~13 Mux6~13clkctrl B[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.876 ns" { enmode enmode~combout mode[1]~reg0 Mux6~13 Mux6~13clkctrl B[0]$latch } { 0.000ns 0.000ns 1.108ns 0.233ns 1.700ns 0.874ns } { 0.000ns 0.799ns 0.712ns 0.225ns 0.000ns 0.225ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "enmode source 2.525 ns - Shortest register " "Info: - Shortest clock path from clock \"enmode\" to source register is 2.525 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.799 ns) 0.799 ns enmode 1 CLK PIN_C13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_C13; Fanout = 2; CLK Node = 'enmode'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { enmode } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.108 ns) + CELL(0.618 ns) 2.525 ns mode\[0\]~reg0 2 REG LCFF_X18_Y19_N15 7 " "Info: 2: + IC(1.108 ns) + CELL(0.618 ns) = 2.525 ns; Loc. = LCFF_X18_Y19_N15; Fanout = 7; REG Node = 'mode\[0\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.726 ns" { enmode mode[0]~reg0 } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 87 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.417 ns ( 56.12 % ) " "Info: Total cell delay = 1.417 ns ( 56.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.108 ns ( 43.88 % ) " "Info: Total interconnect delay = 1.108 ns ( 43.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.525 ns" { enmode mode[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.525 ns" { enmode enmode~combout mode[0]~reg0 } { 0.000ns 0.000ns 1.108ns } { 0.000ns 0.799ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.876 ns" { enmode mode[1]~reg0 Mux6~13 Mux6~13clkctrl B[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.876 ns" { enmode enmode~combout mode[1]~reg0 Mux6~13 Mux6~13clkctrl B[0]$latch } { 0.000ns 0.000ns 1.108ns 0.233ns 1.700ns 0.874ns } { 0.000ns 0.799ns 0.712ns 0.225ns 0.000ns 0.225ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.525 ns" { enmode mode[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.525 ns" { enmode enmode~combout mode[0]~reg0 } { 0.000ns 0.000ns 1.108ns } { 0.000ns 0.799ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns - " "Info: - Micro clock to output delay of source is 0.094 ns" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 87 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.960 ns - Shortest register register " "Info: - Shortest register to register delay is 0.960 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mode\[0\]~reg0 1 REG LCFF_X18_Y19_N15 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y19_N15; Fanout = 7; REG Node = 'mode\[0\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode[0]~reg0 } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 87 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.228 ns) 0.494 ns Mux9~69 2 COMB LCCOMB_X18_Y19_N6 1 " "Info: 2: + IC(0.266 ns) + CELL(0.228 ns) = 0.494 ns; Loc. = LCCOMB_X18_Y19_N6; Fanout = 1; COMB Node = 'Mux9~69'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.494 ns" { mode[0]~reg0 Mux9~69 } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.228 ns) 0.960 ns B\[0\]\$latch 3 REG LCCOMB_X18_Y19_N4 8 " "Info: 3: + IC(0.238 ns) + CELL(0.228 ns) = 0.960 ns; Loc. = LCCOMB_X18_Y19_N4; Fanout = 8; REG Node = 'B\[0\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.466 ns" { Mux9~69 B[0]$latch } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.456 ns ( 47.50 % ) " "Info: Total cell delay = 0.456 ns ( 47.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.504 ns ( 52.50 % ) " "Info: Total interconnect delay = 0.504 ns ( 52.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.960 ns" { mode[0]~reg0 Mux9~69 B[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.960 ns" { mode[0]~reg0 Mux9~69 B[0]$latch } { 0.000ns 0.266ns 0.238ns } { 0.000ns 0.228ns 0.228ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.876 ns" { enmode mode[1]~reg0 Mux6~13 Mux6~13clkctrl B[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.876 ns" { enmode enmode~combout mode[1]~reg0 Mux6~13 Mux6~13clkctrl B[0]$latch } { 0.000ns 0.000ns 1.108ns 0.233ns 1.700ns 0.874ns } { 0.000ns 0.799ns 0.712ns 0.225ns 0.000ns 0.225ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.525 ns" { enmode mode[0]~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.525 ns" { enmode enmode~combout mode[0]~reg0 } { 0.000ns 0.000ns 1.108ns } { 0.000ns 0.799ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.960 ns" { mode[0]~reg0 Mux9~69 B[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.960 ns" { mode[0]~reg0 Mux9~69 B[0]$latch } { 0.000ns 0.266ns 0.238ns } { 0.000ns 0.228ns 0.228ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "enmode G\[3\] G\[0\]\$latch 10.896 ns register " "Info: tco from clock \"enmode\" to destination pin \"G\[3\]\" through register \"G\[0\]\$latch\" is 10.896 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "enmode source 5.877 ns + Longest register " "Info: + Longest clock path from clock \"enmode\" to source register is 5.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.799 ns) 0.799 ns enmode 1 CLK PIN_C13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_C13; Fanout = 2; CLK Node = 'enmode'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { enmode } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.108 ns) + CELL(0.712 ns) 2.619 ns mode\[1\]~reg0 2 REG LCFF_X18_Y19_N13 7 " "Info: 2: + IC(1.108 ns) + CELL(0.712 ns) = 2.619 ns; Loc. = LCFF_X18_Y19_N13; Fanout = 7; REG Node = 'mode\[1\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.820 ns" { enmode mode[1]~reg0 } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 87 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.233 ns) + CELL(0.225 ns) 3.077 ns Mux6~13 3 COMB LCCOMB_X18_Y19_N18 1 " "Info: 3: + IC(0.233 ns) + CELL(0.225 ns) = 3.077 ns; Loc. = LCCOMB_X18_Y19_N18; Fanout = 1; COMB Node = 'Mux6~13'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { mode[1]~reg0 Mux6~13 } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.000 ns) 4.777 ns Mux6~13clkctrl 4 COMB CLKCTRL_G13 3 " "Info: 4: + IC(1.700 ns) + CELL(0.000 ns) = 4.777 ns; Loc. = CLKCTRL_G13; Fanout = 3; COMB Node = 'Mux6~13clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { Mux6~13 Mux6~13clkctrl } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.875 ns) + CELL(0.225 ns) 5.877 ns G\[0\]\$latch 5 REG LCCOMB_X18_Y19_N0 8 " "Info: 5: + IC(0.875 ns) + CELL(0.225 ns) = 5.877 ns; Loc. = LCCOMB_X18_Y19_N0; Fanout = 8; REG Node = 'G\[0\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { Mux6~13clkctrl G[0]$latch } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.961 ns ( 33.37 % ) " "Info: Total cell delay = 1.961 ns ( 33.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.916 ns ( 66.63 % ) " "Info: Total interconnect delay = 3.916 ns ( 66.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.877 ns" { enmode mode[1]~reg0 Mux6~13 Mux6~13clkctrl G[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.877 ns" { enmode enmode~combout mode[1]~reg0 Mux6~13 Mux6~13clkctrl G[0]$latch } { 0.000ns 0.000ns 1.108ns 0.233ns 1.700ns 0.875ns } { 0.000ns 0.799ns 0.712ns 0.225ns 0.000ns 0.225ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.019 ns + Longest register pin " "Info: + Longest register to pin delay is 5.019 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns G\[0\]\$latch 1 REG LCCOMB_X18_Y19_N0 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X18_Y19_N0; Fanout = 8; REG Node = 'G\[0\]\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { G[0]$latch } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.905 ns) + CELL(2.114 ns) 5.019 ns G\[3\] 2 PIN PIN_N7 0 " "Info: 2: + IC(2.905 ns) + CELL(2.114 ns) = 5.019 ns; Loc. = PIN_N7; Fanout = 0; PIN Node = 'G\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.019 ns" { G[0]$latch G[3] } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.114 ns ( 42.12 % ) " "Info: Total cell delay = 2.114 ns ( 42.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.905 ns ( 57.88 % ) " "Info: Total interconnect delay = 2.905 ns ( 57.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.019 ns" { G[0]$latch G[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.019 ns" { G[0]$latch G[3] } { 0.000ns 2.905ns } { 0.000ns 2.114ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.877 ns" { enmode mode[1]~reg0 Mux6~13 Mux6~13clkctrl G[0]$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.877 ns" { enmode enmode~combout mode[1]~reg0 Mux6~13 Mux6~13clkctrl G[0]$latch } { 0.000ns 0.000ns 1.108ns 0.233ns 1.700ns 0.875ns } { 0.000ns 0.799ns 0.712ns 0.225ns 0.000ns 0.225ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.019 ns" { G[0]$latch G[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.019 ns" { G[0]$latch G[3] } { 0.000ns 2.905ns } { 0.000ns 2.114ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 7 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 14 10:44:34 2008 " "Info: Processing ended: Wed May 14 10:44:34 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}