prev_cmp_vga_colour_bar.tan.qmsg

来自「用verilog hdl实现的VGA显示彩条信号」· QMSG 代码 · 共 13 行 · 第 1/4 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 14 10:44:31 2008 " "Info: Processing started: Wed May 14 10:44:31 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga_colour_bar -c vga_colour_bar --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_colour_bar -c vga_colour_bar --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "R\[0\]\$latch " "Warning: Node \"R\[0\]\$latch\" is a latch" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "G\[0\]\$latch " "Warning: Node \"G\[0\]\$latch\" is a latch" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "B\[0\]\$latch " "Warning: Node \"B\[0\]\$latch\" is a latch" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}