vga_colour_bar.map.qmsg

用verilog hdl实现的VGA显示彩条信号

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "R\[6\] vga_colour_bar.v(103) " "Info (10041): Inferred latch for \"R\[6\]\" at vga_colour_bar.v(103)" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "R\[7\] vga_colour_bar.v(103) " "Info (10041): Inferred latch for \"R\[7\]\" at vga_colour_bar.v(103)" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "h_state\[2\]~reg0 " "Warning: No clock transition on \"h_state\[2\]~reg0\" register due to stuck clock or clock enable" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "h_state\[2\]~reg0 clock_enable GND " "Warning: Reduced register \"h_state\[2\]~reg0\" with stuck clock_enable port to stuck value GND" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "v_state\[2\]~reg0 High " "Info: Power-up level of register \"v_state\[2\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "v_state\[2\]~reg0 data_in VCC " "Warning: Reduced register \"v_state\[2\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "v_state\[0\]~reg0 " "Warning: No clock transition on \"v_state\[0\]~reg0\" register due to stuck clock or clock enable" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "v_state\[0\]~reg0 clock_enable GND " "Warning: Reduced register \"v_state\[0\]~reg0\" with stuck clock_enable port to stuck value GND" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "v_state\[1\]~reg0 " "Warning: No clock transition on \"v_state\[1\]~reg0\" register due to stuck clock or clock enable" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "v_state\[1\]~reg0 clock_enable GND " "Warning: Reduced register \"v_state\[1\]~reg0\" with stuck clock_enable port to stuck value GND" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_LATCH_INFO_HDR" "" "Info: Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IOPT_MLS_DUP_LATCH_INFO" "R\[1\]\$latch R\[0\]\$latch " "Info: Duplicate LATCH primitive \"R\[1\]\$latch\" merged with LATCH primitive \"R\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "R\[2\]\$latch R\[0\]\$latch " "Info: Duplicate LATCH primitive \"R\[2\]\$latch\" merged with LATCH primitive \"R\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "R\[3\]\$latch R\[0\]\$latch " "Info: Duplicate LATCH primitive \"R\[3\]\$latch\" merged with LATCH primitive \"R\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "R\[4\]\$latch R\[0\]\$latch " "Info: Duplicate LATCH primitive \"R\[4\]\$latch\" merged with LATCH primitive \"R\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "R\[5\]\$latch R\[0\]\$latch " "Info: Duplicate LATCH primitive \"R\[5\]\$latch\" merged with LATCH primitive \"R\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "R\[6\]\$latch R\[0\]\$latch " "Info: Duplicate LATCH primitive \"R\[6\]\$latch\" merged with LATCH primitive \"R\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "R\[7\]\$latch R\[0\]\$latch " "Info: Duplicate LATCH primitive \"R\[7\]\$latch\" merged with LATCH primitive \"R\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "G\[1\]\$latch G\[0\]\$latch " "Info: Duplicate LATCH primitive \"G\[1\]\$latch\" merged with LATCH primitive \"G\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "G\[2\]\$latch G\[0\]\$latch " "Info: Duplicate LATCH primitive \"G\[2\]\$latch\" merged with LATCH primitive \"G\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "G\[3\]\$latch G\[0\]\$latch " "Info: Duplicate LATCH primitive \"G\[3\]\$latch\" merged with LATCH primitive \"G\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "G\[4\]\$latch G\[0\]\$latch " "Info: Duplicate LATCH primitive \"G\[4\]\$latch\" merged with LATCH primitive \"G\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "G\[5\]\$latch G\[0\]\$latch " "Info: Duplicate LATCH primitive \"G\[5\]\$latch\" merged with LATCH primitive \"G\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "G\[6\]\$latch G\[0\]\$latch " "Info: Duplicate LATCH primitive \"G\[6\]\$latch\" merged with LATCH primitive \"G\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "G\[7\]\$latch G\[0\]\$latch " "Info: Duplicate LATCH primitive \"G\[7\]\$latch\" merged with LATCH primitive \"G\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "B\[1\]\$latch B\[0\]\$latch " "Info: Duplicate LATCH primitive \"B\[1\]\$latch\" merged with LATCH primitive \"B\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "B\[2\]\$latch B\[0\]\$latch " "Info: Duplicate LATCH primitive \"B\[2\]\$latch\" merged with LATCH primitive \"B\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "B\[3\]\$latch B\[0\]\$latch " "Info: Duplicate LATCH primitive \"B\[3\]\$latch\" merged with LATCH primitive \"B\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "B\[4\]\$latch B\[0\]\$latch " "Info: Duplicate LATCH primitive \"B\[4\]\$latch\" merged with LATCH primitive \"B\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "B\[5\]\$latch B\[0\]\$latch " "Info: Duplicate LATCH primitive \"B\[5\]\$latch\" merged with LATCH primitive \"B\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "B\[6\]\$latch B\[0\]\$latch " "Info: Duplicate LATCH primitive \"B\[6\]\$latch\" merged with LATCH primitive \"B\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_LATCH_INFO" "B\[7\]\$latch B\[0\]\$latch " "Info: Duplicate LATCH primitive \"B\[7\]\$latch\" merged with LATCH primitive \"B\[0\]\$latch\"" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate LATCH primitives merged into single LATCH primitive" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "R\[0\]\$latch " "Warning: Latch R\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA mode\[0\]~reg0 " "Warning: Ports D and ENA on the latch are fed by the same signal mode\[0\]~reg0" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 87 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "G\[0\]\$latch " "Warning: Latch G\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA mode\[0\]~reg0 " "Warning: Ports D and ENA on the latch are fed by the same signal mode\[0\]~reg0" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 87 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "B\[0\]\$latch " "Warning: Latch B\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA mode\[0\]~reg0 " "Warning: Ports D and ENA on the latch are fed by the same signal mode\[0\]~reg0" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 87 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "h_state\[2\] GND " "Warning: Pin \"h_state\[2\]\" stuck at GND" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "v_state\[0\] GND " "Warning: Pin \"v_state\[0\]\" stuck at GND" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "v_state\[1\] GND " "Warning: Pin \"v_state\[1\]\" stuck at GND" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "v_state\[2\] VCC " "Warning: Pin \"v_state\[2\]\" stuck at VCC" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 55 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "109 " "Info: Implemented 109 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "58 " "Info: Implemented 58 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "48 " "Info: Implemented 48 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 31 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 16 21:15:16 2008 " "Info: Processing ended: Fri May 16 21:15:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}