vga_colour_bar.map.qmsg

用verilog hdl实现的VGA显示彩条信号

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 16 21:15:10 2008 " "Info: Processing started: Fri May 16 21:15:10 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga_colour_bar -c vga_colour_bar " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_colour_bar -c vga_colour_bar" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_colour_bar.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file vga_colour_bar.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_colour_bar " "Info: Found entity 1: vga_colour_bar" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vga_colour_bar " "Info: Elaborating entity \"vga_colour_bar\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_colour_bar.v(35) " "Warning (10230): Verilog HDL assignment warning at vga_colour_bar.v(35): truncated value with size 32 to match size of target (11)" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 vga_colour_bar.v(43) " "Warning (10230): Verilog HDL assignment warning at vga_colour_bar.v(43): truncated value with size 32 to match size of target (11)" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 43 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "vga_colour_bar.v(59) " "Warning (10270): Verilog HDL Case Statement warning at vga_colour_bar.v(59): incomplete case statement has no default case item" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 59 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h_state vga_colour_bar.v(69) " "Warning (10235): Verilog HDL Always Construct warning at vga_colour_bar.v(69): variable \"h_state\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 69 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "vga_colour_bar.v(69) " "Warning (10270): Verilog HDL Case Statement warning at vga_colour_bar.v(69): incomplete case statement has no default case item" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 69 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 vga_colour_bar.v(90) " "Warning (10230): Verilog HDL assignment warning at vga_colour_bar.v(90): truncated value with size 32 to match size of target (2)" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "vga_colour_bar.v(103) " "Warning (10270): Verilog HDL Case Statement warning at vga_colour_bar.v(103): incomplete case statement has no default case item" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "colourx vga_colour_bar.v(92) " "Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable \"colourx\", which holds its previous value in one or more paths through the always construct" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 92 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "coloury vga_colour_bar.v(92) " "Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable \"coloury\", which holds its previous value in one or more paths through the always construct" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 92 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "colourz vga_colour_bar.v(92) " "Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable \"colourz\", which holds its previous value in one or more paths through the always construct" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 92 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "R vga_colour_bar.v(92) " "Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable \"R\", which holds its previous value in one or more paths through the always construct" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 92 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "G vga_colour_bar.v(92) " "Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable \"G\", which holds its previous value in one or more paths through the always construct" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 92 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "B vga_colour_bar.v(92) " "Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable \"B\", which holds its previous value in one or more paths through the always construct" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 92 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "B\[0\] vga_colour_bar.v(103) " "Info (10041): Inferred latch for \"B\[0\]\" at vga_colour_bar.v(103)" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "B\[1\] vga_colour_bar.v(103) " "Info (10041): Inferred latch for \"B\[1\]\" at vga_colour_bar.v(103)" {  } { { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 103 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}