vga_colour_bar.tan.summary

用verilog hdl实现的VGA显示彩条信号

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.896 ns
From           : G[0]$latch
To             : G[3]
From Clock     : enmode
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 377.64 MHz ( period = 2.648 ns )
From           : v_cnt[10]~reg0
To             : v_cnt[6]~reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'enmode'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : mode[1]~reg0
To             : mode[0]~reg0
From Clock     : enmode
To Clock       : enmode
Failed Paths   : 0

Type           : Clock Hold: 'enmode'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : mode[0]~reg0
To             : B[0]$latch
From Clock     : enmode
To Clock       : enmode
Failed Paths   : 6

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 6

--------------------------------------------------------------------------------------