watch.sch

来自「用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解」· SCH 代码 · 共 13 行

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "virtex2"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
    END NETLIST
    BEGIN SHEET 1 3520 2720
    END SHEET
END SCHEMATIC