stopwatch_translate.vhd

用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解

    port map (
      I0 => xlxn_97(1),
      I1 => xlxn_97(0),
      O => cnt60_t_xlxi_3_t2
    );
  cnt60_t_xlxi_3_i_36_67 : X_AND2
    port map (
      I0 => cnt60_t_xlxn_27,
      I1 => cnt60_t_xlxi_3_tc,
      O => cnt60_t_xlxi_3_ceo
    );
  cnt60_t_xlxi_3_i_36_32 : X_AND3
    port map (
      I0 => xlxn_97(2),
      I1 => xlxn_97(1),
      I2 => xlxn_97(0),
      O => cnt60_t_xlxi_3_t3
    );
  cnt60_t_xlxi_3_i_36_31 : X_AND4
    port map (
      I0 => xlxn_97(3),
      I1 => xlxn_97(2),
      I2 => xlxn_97(1),
      I3 => xlxn_97(0),
      O => cnt60_t_xlxi_3_tc
    );
  cnt60_t_xlxi_3_i_q3_i_36_32 : X_XOR2
    port map (
      I0 => cnt60_t_xlxi_3_t3,
      I1 => xlxn_97(3),
      O => cnt60_t_xlxi_3_i_q3_tq
    );
  cnt60_t_xlxi_3_i_q3_i_36_35 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => cnt60_t_xlxi_3_i_q3_tq,
      RST => cnt60_t_xlxi_3_i_q3_i_36_35_GSR_OR,
      CE => cnt60_t_xlxn_27,
      CLK => clk_int,
      O => xlxn_97(3),
      SET => GND
    );
  cnt60_t_xlxi_3_i_q2_i_36_32 : X_XOR2
    port map (
      I0 => cnt60_t_xlxi_3_t2,
      I1 => xlxn_97(2),
      O => cnt60_t_xlxi_3_i_q2_tq
    );
  cnt60_t_xlxi_3_i_q2_i_36_35 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => cnt60_t_xlxi_3_i_q2_tq,
      RST => cnt60_t_xlxi_3_i_q2_i_36_35_GSR_OR,
      CE => cnt60_t_xlxn_27,
      CLK => clk_int,
      O => xlxn_97(2),
      SET => GND
    );
  cnt60_t_xlxi_3_i_q1_i_36_32 : X_XOR2
    port map (
      I0 => xlxn_97(0),
      I1 => xlxn_97(1),
      O => cnt60_t_xlxi_3_i_q1_tq
    );
  cnt60_t_xlxi_3_i_q1_i_36_35 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => cnt60_t_xlxi_3_i_q1_tq,
      RST => cnt60_t_xlxi_3_i_q1_i_36_35_GSR_OR,
      CE => cnt60_t_xlxn_27,
      CLK => clk_int,
      O => xlxn_97(1),
      SET => GND
    );
  cnt60_t_xlxi_3_i_q0_i_36_32 : X_XOR2
    port map (
      I0 => cnt60_t_xlxi_3_xlxn_1,
      I1 => xlxn_97(0),
      O => cnt60_t_xlxi_3_i_q0_tq
    );
  cnt60_t_xlxi_3_i_q0_i_36_35 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => cnt60_t_xlxi_3_i_q0_tq,
      RST => cnt60_t_xlxi_3_i_q0_i_36_35_GSR_OR,
      CE => cnt60_t_xlxn_27,
      CLK => clk_int,
      O => xlxn_97(0),
      SET => GND
    );
  stmach_t_sreg_ffd1_GSR_OR_32 : X_OR2
    port map (
      I0 => xlxn_3,
      I1 => GSR,
      O => stmach_t_sreg_ffd1_GSR_OR
    );
  stmach_t_sreg_ffd2_GSR_OR_33 : X_OR2
    port map (
      I0 => xlxn_3,
      I1 => GSR,
      O => stmach_t_sreg_ffd2_GSR_OR
    );
  stmach_t_sreg_ffd3_GSR_OR_34 : X_OR2
    port map (
      I0 => xlxn_3,
      I1 => GSR,
      O => stmach_t_sreg_ffd3_GSR_OR
    );
  stmach_t_sreg_ffd6_GSR_OR_35 : X_OR2
    port map (
      I0 => xlxn_3,
      I1 => GSR,
      O => stmach_t_sreg_ffd6_GSR_OR
    );
  stmach_t_sreg_ffd5_GSR_OR_36 : X_OR2
    port map (
      I0 => xlxn_3,
      I1 => GSR,
      O => stmach_t_sreg_ffd5_GSR_OR
    );
  stmach_t_sreg_ffd4_GSR_OR_37 : X_OR2
    port map (
      I0 => xlxn_3,
      I1 => GSR,
      O => stmach_t_sreg_ffd4_GSR_OR
    );
  cnt60_t_xlxi_2_i_q0_GSR_OR_38 : X_OR2
    port map (
      I0 => stmach_t_sreg_ffd1,
      I1 => GSR,
      O => cnt60_t_xlxi_2_i_q0_GSR_OR
    );
  cnt60_t_xlxi_2_i_q1_GSR_OR_39 : X_OR2
    port map (
      I0 => stmach_t_sreg_ffd1,
      I1 => GSR,
      O => cnt60_t_xlxi_2_i_q1_GSR_OR
    );
  cnt60_t_xlxi_2_i_q2_GSR_OR_40 : X_OR2
    port map (
      I0 => stmach_t_sreg_ffd1,
      I1 => GSR,
      O => cnt60_t_xlxi_2_i_q2_GSR_OR
    );
  cnt60_t_xlxi_2_i_q3_GSR_OR_41 : X_OR2
    port map (
      I0 => stmach_t_sreg_ffd1,
      I1 => GSR,
      O => cnt60_t_xlxi_2_i_q3_GSR_OR
    );
  cnt60_t_xlxi_3_i_q3_i_36_35_GSR_OR_42 : X_OR2
    port map (
      I0 => cnt60_t_xlxn_9,
      I1 => GSR,
      O => cnt60_t_xlxi_3_i_q3_i_36_35_GSR_OR
    );
  cnt60_t_xlxi_3_i_q2_i_36_35_GSR_OR_43 : X_OR2
    port map (
      I0 => cnt60_t_xlxn_9,
      I1 => GSR,
      O => cnt60_t_xlxi_3_i_q2_i_36_35_GSR_OR
    );
  cnt60_t_xlxi_3_i_q1_i_36_35_GSR_OR_44 : X_OR2
    port map (
      I0 => cnt60_t_xlxn_9,
      I1 => GSR,
      O => cnt60_t_xlxi_3_i_q1_i_36_35_GSR_OR
    );
  cnt60_t_xlxi_3_i_q0_i_36_35_GSR_OR_45 : X_OR2
    port map (
      I0 => cnt60_t_xlxn_9,
      I1 => GSR,
      O => cnt60_t_xlxi_3_i_q0_i_36_35_GSR_OR
    );
  onesout_6_obuf_GTS_TRI_46 : X_TRI
    port map (
      I => onesout_6_obuf_GTS_TRI,
      CTL => NlwInverterSignal_onesout_6_obuf_GTS_TRI_CTL,
      O => onesout(6)
    );
  onesout_5_obuf_GTS_TRI_47 : X_TRI
    port map (
      I => onesout_5_obuf_GTS_TRI,
      CTL => NlwInverterSignal_onesout_5_obuf_GTS_TRI_CTL,
      O => onesout(5)
    );
  onesout_4_obuf_GTS_TRI_48 : X_TRI
    port map (
      I => onesout_4_obuf_GTS_TRI,
      CTL => NlwInverterSignal_onesout_4_obuf_GTS_TRI_CTL,
      O => onesout(4)
    );
  onesout_3_obuf_GTS_TRI_49 : X_TRI
    port map (
      I => onesout_3_obuf_GTS_TRI,
      CTL => NlwInverterSignal_onesout_3_obuf_GTS_TRI_CTL,
      O => onesout(3)
    );
  onesout_2_obuf_GTS_TRI_50 : X_TRI
    port map (
      I => onesout_2_obuf_GTS_TRI,
      CTL => NlwInverterSignal_onesout_2_obuf_GTS_TRI_CTL,
      O => onesout(2)
    );
  onesout_1_obuf_GTS_TRI_51 : X_TRI
    port map (
      I => onesout_1_obuf_GTS_TRI,
      CTL => NlwInverterSignal_onesout_1_obuf_GTS_TRI_CTL,
      O => onesout(1)
    );
  onesout_0_obuf_GTS_TRI_52 : X_TRI
    port map (
      I => onesout_0_obuf_GTS_TRI,
      CTL => NlwInverterSignal_onesout_0_obuf_GTS_TRI_CTL,
      O => onesout(0)
    );
  tensout_6_obuf_GTS_TRI_53 : X_TRI
    port map (
      I => tensout_6_obuf_GTS_TRI,
      CTL => NlwInverterSignal_tensout_6_obuf_GTS_TRI_CTL,
      O => tensout(6)
    );
  tensout_5_obuf_GTS_TRI_54 : X_TRI
    port map (
      I => tensout_5_obuf_GTS_TRI,
      CTL => NlwInverterSignal_tensout_5_obuf_GTS_TRI_CTL,
      O => tensout(5)
    );
  tensout_4_obuf_GTS_TRI_55 : X_TRI
    port map (
      I => tensout_4_obuf_GTS_TRI,
      CTL => NlwInverterSignal_tensout_4_obuf_GTS_TRI_CTL,
      O => tensout(4)
    );
  tensout_3_obuf_GTS_TRI_56 : X_TRI
    port map (
      I => tensout_3_obuf_GTS_TRI,
      CTL => NlwInverterSignal_tensout_3_obuf_GTS_TRI_CTL,
      O => tensout(3)
    );
  tensout_2_obuf_GTS_TRI_57 : X_TRI
    port map (
      I => tensout_2_obuf_GTS_TRI,
      CTL => NlwInverterSignal_tensout_2_obuf_GTS_TRI_CTL,
      O => tensout(2)
    );
  tensout_1_obuf_GTS_TRI_58 : X_TRI
    port map (
      I => tensout_1_obuf_GTS_TRI,
      CTL => NlwInverterSignal_tensout_1_obuf_GTS_TRI_CTL,
      O => tensout(1)
    );
  tensout_0_obuf_GTS_TRI_59 : X_TRI
    port map (
      I => tensout_0_obuf_GTS_TRI,
      CTL => NlwInverterSignal_tensout_0_obuf_GTS_TRI_CTL,
      O => tensout(0)
    );
  out3_t_i1_GTS_TRI_60 : X_TRI
    port map (
      I => out3_t_i1_GTS_TRI,
      CTL => NlwInverterSignal_out3_t_i1_GTS_TRI_CTL,
      O => tenthsout(9)
    );
  out3_t_i2_GTS_TRI_61 : X_TRI
    port map (
      I => out3_t_i2_GTS_TRI,
      CTL => NlwInverterSignal_out3_t_i2_GTS_TRI_CTL,
      O => tenthsout(8)
    );
  out3_t_i3_GTS_TRI_62 : X_TRI
    port map (
      I => out3_t_i3_GTS_TRI,
      CTL => NlwInverterSignal_out3_t_i3_GTS_TRI_CTL,
      O => tenthsout(7)
    );
  out3_t_i4_GTS_TRI_63 : X_TRI
    port map (
      I => out3_t_i4_GTS_TRI,
      CTL => NlwInverterSignal_out3_t_i4_GTS_TRI_CTL,
      O => tenthsout(6)
    );
  out3_t_i5_GTS_TRI_64 : X_TRI
    port map (
      I => out3_t_i5_GTS_TRI,
      CTL => NlwInverterSignal_out3_t_i5_GTS_TRI_CTL,
      O => tenthsout(5)
    );
  out3_t_i6_GTS_TRI_65 : X_TRI
    port map (
      I => out3_t_i6_GTS_TRI,
      CTL => NlwInverterSignal_out3_t_i6_GTS_TRI_CTL,
      O => tenthsout(4)
    );
  out3_t_i7_GTS_TRI_66 : X_TRI
    port map (
      I => out3_t_i7_GTS_TRI,
      CTL => NlwInverterSignal_out3_t_i7_GTS_TRI_CTL,
      O => tenthsout(3)
    );
  out3_t_i8_GTS_TRI_67 : X_TRI
    port map (
      I => out3_t_i8_GTS_TRI,
      CTL => NlwInverterSignal_out3_t_i8_GTS_TRI_CTL,
      O => tenthsout(2)
    );
  out3_t_i9_GTS_TRI_68 : X_TRI
    port map (
      I => out3_t_i9_GTS_TRI,
      CTL => NlwInverterSignal_out3_t_i9_GTS_TRI_CTL,
      O => tenthsout(1)
    );
  out3_t_i10_GTS_TRI_69 : X_TRI
    port map (
      I => out3_t_i10_GTS_TRI,
      CTL => NlwInverterSignal_out3_t_i10_GTS_TRI_CTL,
      O => tenthsout(0)
    );
  NlwBlock_stopwatch_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_stopwatch_GND : X_ZERO
    port map (
      O => GND
    );
  NlwInverterBlock_cnt60_t_xlxi_2_i_36_81_i0 : X_INV
    port map (
      I => xlxn_96(3),
      O => NlwInverterSignal_cnt60_t_xlxi_2_i_36_81_i0
    );
  NlwInverterBlock_cnt60_t_xlxi_2_i_36_105_i0 : X_INV
    port map (
      I => xlxn_96(2),
      O => NlwInverterSignal_cnt60_t_xlxi_2_i_36_105_i0
    );
  NlwInverterBlock_cnt60_t_xlxi_2_i_36_105_i1 : X_INV
    port map (
      I => xlxn_96(1),
      O => NlwInverterSignal_cnt60_t_xlxi_2_i_36_105_i1
    );
  NlwInverterBlock_onesout_6_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_onesout_6_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_onesout_5_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_onesout_5_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_onesout_4_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_onesout_4_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_onesout_3_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_onesout_3_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_onesout_2_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_onesout_2_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_onesout_1_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_onesout_1_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_onesout_0_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_onesout_0_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_tensout_6_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tensout_6_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_tensout_5_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tensout_5_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_tensout_4_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tensout_4_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_tensout_3_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tensout_3_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_tensout_2_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tensout_2_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_tensout_1_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tensout_1_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_tensout_0_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tensout_0_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_out3_t_i1_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_out3_t_i1_GTS_TRI_CTL
    );
  NlwInverterBlock_out3_t_i2_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_out3_t_i2_GTS_TRI_CTL
    );
  NlwInverterBlock_out3_t_i3_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_out3_t_i3_GTS_TRI_CTL
    );
  NlwInverterBlock_out3_t_i4_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_out3_t_i4_GTS_TRI_CTL
    );
  NlwInverterBlock_out3_t_i5_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_out3_t_i5_GTS_TRI_CTL
    );
  NlwInverterBlock_out3_t_i6_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_out3_t_i6_GTS_TRI_CTL
    );
  NlwInverterBlock_out3_t_i7_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_out3_t_i7_GTS_TRI_CTL
    );
  NlwInverterBlock_out3_t_i8_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_out3_t_i8_GTS_TRI_CTL
    );
  NlwInverterBlock_out3_t_i9_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_out3_t_i9_GTS_TRI_CTL
    );
  NlwInverterBlock_out3_t_i10_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_out3_t_i10_GTS_TRI_CTL
    );
  NlwBlockROC : ROC generic map ( WIDTH => 100 ns)
     port map (O => GSR);
  NlwBlockTOC : TOC     port map (O => GTS);
end Structure;