stopwatch_translate.vhd

用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解

    generic map(
      INIT => X"8492"
    )
    port map (
      ADR0 => xlxn_97(0),
      ADR1 => xlxn_97(1),
      ADR2 => xlxn_97(2),
      ADR3 => xlxn_97(3),
      O => tensout_3_obuf
    );
  hex2led1_mrom_led_inst_lut4_151 : X_LUT4
    generic map(
      INIT => X"208E"
    )
    port map (
      ADR0 => xlxn_96(0),
      ADR1 => xlxn_96(1),
      ADR2 => xlxn_96(2),
      ADR3 => xlxn_96(3),
      O => onesout_5_obuf
    );
  hex2led1_mrom_led_inst_lut4_161 : X_LUT4
    generic map(
      INIT => X"1083"
    )
    port map (
      ADR0 => xlxn_96(0),
      ADR1 => xlxn_96(1),
      ADR2 => xlxn_96(2),
      ADR3 => xlxn_96(3),
      O => onesout_6_obuf
    );
  hex2led1_mrom_led_inst_lut4_101 : X_LUT4
    generic map(
      INIT => X"2812"
    )
    port map (
      ADR0 => xlxn_96(0),
      ADR1 => xlxn_96(1),
      ADR2 => xlxn_96(2),
      ADR3 => xlxn_96(3),
      O => onesout_0_obuf
    );
  hex2led1_mrom_led_inst_lut4_111 : X_LUT4
    generic map(
      INIT => X"D860"
    )
    port map (
      ADR0 => xlxn_96(0),
      ADR1 => xlxn_96(1),
      ADR2 => xlxn_96(2),
      ADR3 => xlxn_96(3),
      O => onesout_1_obuf
    );
  hex2led1_mrom_led_inst_lut4_121 : X_LUT4
    generic map(
      INIT => X"D004"
    )
    port map (
      ADR0 => xlxn_96(0),
      ADR1 => xlxn_96(1),
      ADR2 => xlxn_96(2),
      ADR3 => xlxn_96(3),
      O => onesout_2_obuf
    );
  hex2led1_mrom_led_inst_lut4_131 : X_LUT4
    generic map(
      INIT => X"8492"
    )
    port map (
      ADR0 => xlxn_96(0),
      ADR1 => xlxn_96(1),
      ADR2 => xlxn_96(2),
      ADR3 => xlxn_96(3),
      O => onesout_3_obuf
    );
  out3_t_i1 : X_BUF
    port map (
      I => out3_t_xlxn_12,
      O => out3_t_i1_GTS_TRI
    );
  out3_t_i2 : X_BUF
    port map (
      I => out3_t_xlxn_13,
      O => out3_t_i2_GTS_TRI
    );
  out3_t_i11 : X_INV
    port map (
      I => xlxn_36(0),
      O => out3_t_xlxn_21
    );
  out3_t_i12 : X_INV
    port map (
      I => xlxn_36(9),
      O => out3_t_xlxn_12
    );
  out3_t_i13 : X_INV
    port map (
      I => xlxn_36(8),
      O => out3_t_xlxn_13
    );
  out3_t_i14 : X_INV
    port map (
      I => xlxn_36(7),
      O => out3_t_xlxn_14
    );
  out3_t_i15 : X_INV
    port map (
      I => xlxn_36(6),
      O => out3_t_xlxn_15
    );
  out3_t_i16 : X_INV
    port map (
      I => xlxn_36(5),
      O => out3_t_xlxn_16
    );
  out3_t_i17 : X_INV
    port map (
      I => xlxn_36(4),
      O => out3_t_xlxn_17
    );
  out3_t_i18 : X_INV
    port map (
      I => xlxn_36(3),
      O => out3_t_xlxn_18
    );
  out3_t_i19 : X_INV
    port map (
      I => xlxn_36(2),
      O => out3_t_xlxn_19
    );
  out3_t_i20 : X_INV
    port map (
      I => xlxn_36(1),
      O => out3_t_xlxn_20
    );
  out3_t_i10 : X_BUF
    port map (
      I => out3_t_xlxn_21,
      O => out3_t_i10_GTS_TRI
    );
  out3_t_i9 : X_BUF
    port map (
      I => out3_t_xlxn_20,
      O => out3_t_i9_GTS_TRI
    );
  out3_t_i8 : X_BUF
    port map (
      I => out3_t_xlxn_19,
      O => out3_t_i8_GTS_TRI
    );
  out3_t_i7 : X_BUF
    port map (
      I => out3_t_xlxn_18,
      O => out3_t_i7_GTS_TRI
    );
  out3_t_i6 : X_BUF
    port map (
      I => out3_t_xlxn_17,
      O => out3_t_i6_GTS_TRI
    );
  out3_t_i5 : X_BUF
    port map (
      I => out3_t_xlxn_16,
      O => out3_t_i5_GTS_TRI
    );
  out3_t_i4 : X_BUF
    port map (
      I => out3_t_xlxn_15,
      O => out3_t_i4_GTS_TRI
    );
  stmach_t_sreg_ffd2_10 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => stmach_t_sreg_xx_ffd2,
      RST => stmach_t_sreg_ffd2_GSR_OR,
      CLK => clk_int,
      O => stmach_t_sreg_ffd2,
      CE => VCC,
      SET => GND
    );
  stmach_t_sreg_ffd3_11 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => stmach_t_sreg_xx_ffd3,
      RST => stmach_t_sreg_ffd3_GSR_OR,
      CLK => clk_int,
      O => stmach_t_sreg_ffd3,
      CE => VCC,
      SET => GND
    );
  stmach_t_sreg_ffd6_12 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => stmach_t_sreg_xx_ffd6,
      RST => stmach_t_sreg_ffd6_GSR_OR,
      CLK => clk_int,
      O => stmach_t_sreg_ffd6,
      CE => VCC,
      SET => GND
    );
  stmach_t_sreg_ffd5_13 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => stmach_t_sreg_xx_ffd5,
      RST => stmach_t_sreg_ffd5_GSR_OR,
      CLK => clk_int,
      O => stmach_t_sreg_ffd5,
      CE => VCC,
      SET => GND
    );
  stmach_t_sreg_ffd4_14 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => stmach_t_sreg_xx_ffd4,
      RST => stmach_t_sreg_ffd4_GSR_OR,
      CLK => clk_int,
      O => stmach_t_sreg_ffd4,
      CE => VCC,
      SET => GND
    );
  stmach_t_sreg_xx_ffd61 : X_LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      ADR0 => stmach_t_sreg_ffd1,
      ADR1 => xlxn_5,
      ADR2 => stmach_t_sreg_ffd6,
      O => stmach_t_sreg_xx_ffd6
    );
  stmach_t_sreg_xx_ffd51 : X_LUT3
    generic map(
      INIT => X"54"
    )
    port map (
      ADR0 => xlxn_5,
      ADR1 => stmach_t_sreg_ffd4,
      ADR2 => stmach_t_sreg_ffd5,
      O => stmach_t_sreg_xx_ffd5
    );
  stmach_t_sreg_xx_ffd41 : X_LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      ADR0 => xlxn_5,
      ADR1 => stmach_t_sreg_ffd2,
      ADR2 => stmach_t_sreg_ffd4,
      O => stmach_t_sreg_xx_ffd4
    );
  stmach_t_sreg_xx_ffd31 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => xlxn_5,
      ADR1 => stmach_t_sreg_ffd6,
      ADR2 => stmach_t_sreg_ffd3,
      ADR3 => stmach_t_sreg_ffd5,
      O => stmach_t_sreg_xx_ffd3
    );
  tensout_0_obuf_15 : X_BUF
    port map (
      I => tensout_0_obuf,
      O => tensout_0_obuf_GTS_TRI
    );
  onesout_6_obuf_16 : X_BUF
    port map (
      I => onesout_6_obuf,
      O => onesout_6_obuf_GTS_TRI
    );
  onesout_5_obuf_17 : X_BUF
    port map (
      I => onesout_5_obuf,
      O => onesout_5_obuf_GTS_TRI
    );
  onesout_4_obuf_18 : X_BUF
    port map (
      I => onesout_4_obuf,
      O => onesout_4_obuf_GTS_TRI
    );
  onesout_3_obuf_19 : X_BUF
    port map (
      I => onesout_3_obuf,
      O => onesout_3_obuf_GTS_TRI
    );
  onesout_2_obuf_20 : X_BUF
    port map (
      I => onesout_2_obuf,
      O => onesout_2_obuf_GTS_TRI
    );
  onesout_1_obuf_21 : X_BUF
    port map (
      I => onesout_1_obuf,
      O => onesout_1_obuf_GTS_TRI
    );
  onesout_0_obuf_22 : X_BUF
    port map (
      I => onesout_0_obuf,
      O => onesout_0_obuf_GTS_TRI
    );
  tensout_6_obuf_23 : X_BUF
    port map (
      I => tensout_6_obuf,
      O => tensout_6_obuf_GTS_TRI
    );
  tensout_5_obuf_24 : X_BUF
    port map (
      I => tensout_5_obuf,
      O => tensout_5_obuf_GTS_TRI
    );
  tensout_4_obuf_25 : X_BUF
    port map (
      I => tensout_4_obuf,
      O => tensout_4_obuf_GTS_TRI
    );
  tensout_3_obuf_26 : X_BUF
    port map (
      I => tensout_3_obuf,
      O => tensout_3_obuf_GTS_TRI
    );
  tensout_2_obuf_27 : X_BUF
    port map (
      I => tensout_2_obuf,
      O => tensout_2_obuf_GTS_TRI
    );
  tensout_1_obuf_28 : X_BUF
    port map (
      I => tensout_1_obuf,
      O => tensout_1_obuf_GTS_TRI
    );
  stmach_t_clkout1 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => stmach_t_sreg_ffd2,
      ADR1 => stmach_t_sreg_ffd3,
      O => stmach_t_clkout1_O
    );
  stmach_t_clkout1_LUT2_L_BUF : X_BUF
    port map (
      I => stmach_t_clkout1_O,
      O => clken_int
    );
  cnt60_t_xlxi_2_i_36_73 : X_XOR2
    port map (
      I0 => xlxn_96(3),
      I1 => cnt60_t_xlxi_2_ox3,
      O => cnt60_t_xlxi_2_d3
    );
  cnt60_t_xlxi_2_i_36_78 : X_XOR2
    port map (
      I0 => xlxn_96(2),
      I1 => cnt60_t_xlxi_2_ax2,
      O => cnt60_t_xlxi_2_d2
    );
  cnt60_t_xlxi_2_i_36_86 : X_XOR2
    port map (
      I0 => xlxn_96(1),
      I1 => cnt60_t_xlxi_2_ax1,
      O => cnt60_t_xlxi_2_d1
    );
  cnt60_t_xlxi_2_i_36_75 : X_OR2
    port map (
      I0 => cnt60_t_xlxi_2_ao3a,
      I1 => cnt60_t_xlxi_2_a03b,
      O => cnt60_t_xlxi_2_ox3
    );
  cnt60_t_xlxi_2_i_36_83 : X_INV
    port map (
      I => xlxn_96(0),
      O => cnt60_t_xlxi_2_d0
    );
  cnt60_t_xlxi_2_i_36_88 : X_AND2
    port map (
      I0 => xlxn_96(3),
      I1 => xlxn_96(0),
      O => cnt60_t_xlxi_2_ao3a
    );
  cnt60_t_xlxi_2_i_36_77 : X_AND2
    port map (
      I0 => xlxn_96(0),
      I1 => xlxn_96(1),
      O => cnt60_t_xlxi_2_ax2
    );
  cnt60_t_xlxi_2_i_36_99 : X_AND2
    port map (
      I0 => xlxn_95,
      I1 => cnt60_t_xlxn_8,
      O => cnt60_t_xlxi_2_ceo
    );
  cnt60_t_xlxi_2_i_36_81 : X_AND2
    port map (
      I0 => NlwInverterSignal_cnt60_t_xlxi_2_i_36_81_i0,
      I1 => xlxn_96(0),
      O => cnt60_t_xlxi_2_ax1
    );
  cnt60_t_xlxi_2_i_36_70 : X_AND3
    port map (
      I0 => xlxn_96(2),
      I1 => xlxn_96(0),
      I2 => xlxn_96(1),
      O => cnt60_t_xlxi_2_a03b
    );
  cnt60_t_xlxi_2_i_36_105 : X_AND4
    port map (
      I0 => NlwInverterSignal_cnt60_t_xlxi_2_i_36_105_i0,
      I1 => NlwInverterSignal_cnt60_t_xlxi_2_i_36_105_i1,
      I2 => xlxn_96(0),
      I3 => xlxn_96(3),
      O => cnt60_t_xlxn_8
    );
  cnt60_t_xlxi_2_i_q0 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => cnt60_t_xlxi_2_d0,
      RST => cnt60_t_xlxi_2_i_q0_GSR_OR,
      CE => xlxn_95,
      CLK => clk_int,
      O => xlxn_96(0),
      SET => GND
    );
  cnt60_t_xlxi_2_i_q1 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => cnt60_t_xlxi_2_d1,
      RST => cnt60_t_xlxi_2_i_q1_GSR_OR,
      CE => xlxn_95,
      CLK => clk_int,
      O => xlxn_96(1),
      SET => GND
    );
  cnt60_t_xlxi_2_i_q2 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => cnt60_t_xlxi_2_d2,
      RST => cnt60_t_xlxi_2_i_q2_GSR_OR,
      CE => xlxn_95,
      CLK => clk_int,
      O => xlxn_96(2),
      SET => GND
    );
  cnt60_t_xlxi_2_i_q3 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => cnt60_t_xlxi_2_d3,
      RST => cnt60_t_xlxi_2_i_q3_GSR_OR,
      CE => xlxn_95,
      CLK => clk_int,
      O => xlxn_96(3),
      SET => GND
    );
  cnt60_t_xlxi_3_i_36_58 : X_ONE
    port map (
      O => cnt60_t_xlxi_3_xlxn_1
    );
  cnt60_t_xlxi_3_i_36_33 : X_AND2