stopwatch_translate.vhd

用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解

  signal cnt60_t_xlxn_16 : STD_LOGIC; 
  signal cnt60_t_xlxn_27 : STD_LOGIC; 
  signal cnt60_t_xlxn_26 : STD_LOGIC; 
  signal cnt60_t_xlxn_24 : STD_LOGIC; 
  signal cnt60_t_xlxn_8 : STD_LOGIC; 
  signal cnt60_t_xlxn_9 : STD_LOGIC; 
  signal out3_t_xlxn_20 : STD_LOGIC; 
  signal out3_t_xlxn_21 : STD_LOGIC; 
  signal out3_t_xlxn_19 : STD_LOGIC; 
  signal out3_t_xlxn_12 : STD_LOGIC; 
  signal out3_t_xlxn_13 : STD_LOGIC; 
  signal out3_t_xlxn_14 : STD_LOGIC; 
  signal out3_t_xlxn_15 : STD_LOGIC; 
  signal out3_t_xlxn_16 : STD_LOGIC; 
  signal out3_t_xlxn_17 : STD_LOGIC; 
  signal out3_t_xlxn_18 : STD_LOGIC; 
  signal stmach_t_sreg_xx_ffd6 : STD_LOGIC; 
  signal stmach_t_sreg_ffd4 : STD_LOGIC; 
  signal stmach_t_sreg_xx_ffd3 : STD_LOGIC; 
  signal stmach_t_sreg_xx_ffd2 : STD_LOGIC; 
  signal stmach_t_sreg_ffd5 : STD_LOGIC; 
  signal stmach_t_sreg_ffd6 : STD_LOGIC; 
  signal stmach_t_sreg_ffd2 : STD_LOGIC; 
  signal stmach_t_sreg_ffd3 : STD_LOGIC; 
  signal stmach_t_sreg_xx_ffd4 : STD_LOGIC; 
  signal stmach_t_sreg_xx_ffd5 : STD_LOGIC; 
  signal stmach_t_clkout1_O : STD_LOGIC; 
  signal cnt60_t_xlxi_2_ceo : STD_LOGIC; 
  signal cnt60_t_xlxi_2_a03b : STD_LOGIC; 
  signal cnt60_t_xlxi_2_ao3a : STD_LOGIC; 
  signal cnt60_t_xlxi_2_ax1 : STD_LOGIC; 
  signal cnt60_t_xlxi_2_ax2 : STD_LOGIC; 
  signal cnt60_t_xlxi_2_d0 : STD_LOGIC; 
  signal cnt60_t_xlxi_2_d1 : STD_LOGIC; 
  signal cnt60_t_xlxi_2_d2 : STD_LOGIC; 
  signal cnt60_t_xlxi_2_d3 : STD_LOGIC; 
  signal cnt60_t_xlxi_2_ox3 : STD_LOGIC; 
  signal cnt60_t_xlxi_3_ceo : STD_LOGIC; 
  signal cnt60_t_xlxi_3_xlxn_1 : STD_LOGIC; 
  signal cnt60_t_xlxi_3_tc : STD_LOGIC; 
  signal cnt60_t_xlxi_3_t3 : STD_LOGIC; 
  signal cnt60_t_xlxi_3_t2 : STD_LOGIC; 
  signal cnt60_t_xlxi_3_i_q3_tq : STD_LOGIC; 
  signal cnt60_t_xlxi_3_i_q2_tq : STD_LOGIC; 
  signal cnt60_t_xlxi_3_i_q1_tq : STD_LOGIC; 
  signal cnt60_t_xlxi_3_i_q0_tq : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal stmach_t_sreg_ffd1_GSR_OR : STD_LOGIC; 
  signal stmach_t_sreg_ffd2_GSR_OR : STD_LOGIC; 
  signal stmach_t_sreg_ffd3_GSR_OR : STD_LOGIC; 
  signal stmach_t_sreg_ffd6_GSR_OR : STD_LOGIC; 
  signal stmach_t_sreg_ffd5_GSR_OR : STD_LOGIC; 
  signal stmach_t_sreg_ffd4_GSR_OR : STD_LOGIC; 
  signal cnt60_t_xlxi_2_i_q0_GSR_OR : STD_LOGIC; 
  signal cnt60_t_xlxi_2_i_q1_GSR_OR : STD_LOGIC; 
  signal cnt60_t_xlxi_2_i_q2_GSR_OR : STD_LOGIC; 
  signal cnt60_t_xlxi_2_i_q3_GSR_OR : STD_LOGIC; 
  signal cnt60_t_xlxi_3_i_q3_i_36_35_GSR_OR : STD_LOGIC; 
  signal cnt60_t_xlxi_3_i_q2_i_36_35_GSR_OR : STD_LOGIC; 
  signal cnt60_t_xlxi_3_i_q1_i_36_35_GSR_OR : STD_LOGIC; 
  signal cnt60_t_xlxi_3_i_q0_i_36_35_GSR_OR : STD_LOGIC; 
  signal onesout_6_obuf_GTS_TRI : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal onesout_5_obuf_GTS_TRI : STD_LOGIC; 
  signal onesout_4_obuf_GTS_TRI : STD_LOGIC; 
  signal onesout_3_obuf_GTS_TRI : STD_LOGIC; 
  signal onesout_2_obuf_GTS_TRI : STD_LOGIC; 
  signal onesout_1_obuf_GTS_TRI : STD_LOGIC; 
  signal onesout_0_obuf_GTS_TRI : STD_LOGIC; 
  signal tensout_6_obuf_GTS_TRI : STD_LOGIC; 
  signal tensout_5_obuf_GTS_TRI : STD_LOGIC; 
  signal tensout_4_obuf_GTS_TRI : STD_LOGIC; 
  signal tensout_3_obuf_GTS_TRI : STD_LOGIC; 
  signal tensout_2_obuf_GTS_TRI : STD_LOGIC; 
  signal tensout_1_obuf_GTS_TRI : STD_LOGIC; 
  signal tensout_0_obuf_GTS_TRI : STD_LOGIC; 
  signal out3_t_i1_GTS_TRI : STD_LOGIC; 
  signal out3_t_i2_GTS_TRI : STD_LOGIC; 
  signal out3_t_i3_GTS_TRI : STD_LOGIC; 
  signal out3_t_i4_GTS_TRI : STD_LOGIC; 
  signal out3_t_i5_GTS_TRI : STD_LOGIC; 
  signal out3_t_i6_GTS_TRI : STD_LOGIC; 
  signal out3_t_i7_GTS_TRI : STD_LOGIC; 
  signal out3_t_i8_GTS_TRI : STD_LOGIC; 
  signal out3_t_i9_GTS_TRI : STD_LOGIC; 
  signal out3_t_i10_GTS_TRI : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_CLK90_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_CLK180_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_CLK270_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_CLK2X_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_CLK2X180_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_CLKDV_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_CLKFX_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_CLKFX180_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_LOCKED_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_PSDONE_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_STATUS_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_STATUS_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_STATUS_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_STATUS_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_STATUS_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_STATUS_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_STATUS_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dcm1_t_dcm_inst_STATUS_0_UNCONNECTED : STD_LOGIC; 
  signal NlwInverterSignal_cnt60_t_xlxi_2_i_36_81_i0 : STD_LOGIC; 
  signal NlwInverterSignal_cnt60_t_xlxi_2_i_36_105_i0 : STD_LOGIC; 
  signal NlwInverterSignal_cnt60_t_xlxi_2_i_36_105_i1 : STD_LOGIC; 
  signal NlwInverterSignal_onesout_6_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_onesout_5_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_onesout_4_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_onesout_3_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_onesout_2_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_onesout_1_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_onesout_0_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_tensout_6_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_tensout_5_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_tensout_4_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_tensout_3_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_tensout_2_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_tensout_1_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_tensout_0_obuf_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_out3_t_i1_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_out3_t_i2_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_out3_t_i3_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_out3_t_i4_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_out3_t_i5_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_out3_t_i6_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_out3_t_i7_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_out3_t_i8_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_out3_t_i9_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_out3_t_i10_GTS_TRI_CTL : STD_LOGIC; 
  signal xlxn_36 : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal xlxn_96 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal xlxn_97 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal xlxn_35 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  xlxi_22 : X_AND2
    port map (
      I0 => clken_int,
      I1 => xlxn_105,
      O => xlxn_95
    );
  dcm1_t_clkin_ibufg_inst : X_CKBUF
    port map (
      I => clk,
      O => dcm1_t_clkin_ibufg
    );
  decode_t_mrom_one_hot_inst_lut4_81 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => xlxn_35(0),
      ADR1 => xlxn_35(3),
      ADR2 => xlxn_35(1),
      ADR3 => xlxn_35(2),
      O => xlxn_36(8)
    );
  hex2led2_mrom_led_inst_lut4_141 : X_LUT4
    generic map(
      INIT => X"02BA"
    )
    port map (
      ADR0 => xlxn_97(0),
      ADR1 => xlxn_97(1),
      ADR2 => xlxn_97(2),
      ADR3 => xlxn_97(3),
      O => tensout_4_obuf
    );
  hex2led1_mrom_led_inst_lut4_141 : X_LUT4
    generic map(
      INIT => X"02BA"
    )
    port map (
      ADR0 => xlxn_96(0),
      ADR1 => xlxn_96(1),
      ADR2 => xlxn_96(2),
      ADR3 => xlxn_96(3),
      O => onesout_4_obuf
    );
  xlxi_11 : X_BUF
    port map (
      I => starstop,
      O => xlxn_5
    );
  xlxi_10 : X_BUF
    port map (
      I => reset,
      O => xlxn_2
    );
  xlxi_9 : X_INV
    port map (
      I => xlxn_2,
      O => xlxn_3
    );
  out3_t_i3 : X_BUF
    port map (
      I => out3_t_xlxn_14,
      O => out3_t_i3_GTS_TRI
    );
  stmach_t_sreg_ffd1_9 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => n579,
      SET => stmach_t_sreg_ffd1_GSR_OR,
      CLK => clk_int,
      O => stmach_t_sreg_ffd1,
      CE => VCC,
      RST => GND
    );
  tenths_t : tenths
    port map (
      ce => clken_int,
      clk => clk_int,
      ainit => stmach_t_sreg_ffd1,
      q_thresh0 => xlxn_105,
      GSR => GSR,
      q(3) => xlxn_35(3),
      q(2) => xlxn_35(2),
      q(1) => xlxn_35(1),
      q(0) => xlxn_35(0)
    );
  dcm1_t_clk0_bufg_inst : X_CKBUF
    port map (
      I => dcm1_t_clk0_buf,
      O => clk_int
    );
  xst_gnd : X_ZERO
    port map (
      O => n579
    );
  dcm1_t_dcm_inst : X_DCM
    generic map(
      CLK_FEEDBACK => "1X",
      CLKDV_DIVIDE => 2.0,
      CLKFX_DIVIDE => 1,
      CLKFX_MULTIPLY => 4,
      CLKIN_DIVIDE_BY_2 => false,
      CLKOUT_PHASE_SHIFT => "NONE",
      DFS_FREQUENCY_MODE => "LOW",
      DLL_FREQUENCY_MODE => "LOW",
      DUTY_CYCLE_CORRECTION => true,
      PHASE_SHIFT => 0
    )
    port map (
      RST => n579,
      CLKIN => dcm1_t_clkin_ibufg,
      CLKFB => clk_int,
      PSINCDEC => n579,
      PSEN => n579,
      PSCLK => n579,
      DSSEN => n579,
      CLK0 => dcm1_t_clk0_buf,
      CLK90 => NLW_dcm1_t_dcm_inst_CLK90_UNCONNECTED,
      CLK180 => NLW_dcm1_t_dcm_inst_CLK180_UNCONNECTED,
      CLK270 => NLW_dcm1_t_dcm_inst_CLK270_UNCONNECTED,
      CLK2X => NLW_dcm1_t_dcm_inst_CLK2X_UNCONNECTED,
      CLK2X180 => NLW_dcm1_t_dcm_inst_CLK2X180_UNCONNECTED,
      CLKDV => NLW_dcm1_t_dcm_inst_CLKDV_UNCONNECTED,
      CLKFX => NLW_dcm1_t_dcm_inst_CLKFX_UNCONNECTED,
      CLKFX180 => NLW_dcm1_t_dcm_inst_CLKFX180_UNCONNECTED,
      LOCKED => NLW_dcm1_t_dcm_inst_LOCKED_UNCONNECTED,
      PSDONE => NLW_dcm1_t_dcm_inst_PSDONE_UNCONNECTED,
      STATUS(7) => NLW_dcm1_t_dcm_inst_STATUS_7_UNCONNECTED,
      STATUS(6) => NLW_dcm1_t_dcm_inst_STATUS_6_UNCONNECTED,
      STATUS(5) => NLW_dcm1_t_dcm_inst_STATUS_5_UNCONNECTED,
      STATUS(4) => NLW_dcm1_t_dcm_inst_STATUS_4_UNCONNECTED,
      STATUS(3) => NLW_dcm1_t_dcm_inst_STATUS_3_UNCONNECTED,
      STATUS(2) => NLW_dcm1_t_dcm_inst_STATUS_2_UNCONNECTED,
      STATUS(1) => NLW_dcm1_t_dcm_inst_STATUS_1_UNCONNECTED,
      STATUS(0) => NLW_dcm1_t_dcm_inst_STATUS_0_UNCONNECTED
    );
  cnt60_t_xlxi_4 : X_OR2
    port map (
      I0 => cnt60_t_xlxn_26,
      I1 => stmach_t_sreg_ffd1,
      O => cnt60_t_xlxn_9
    );
  cnt60_t_xlxi_8 : X_INV
    port map (
      I => xlxn_97(3),
      O => cnt60_t_xlxn_15
    );
  cnt60_t_xlxi_5 : X_INV
    port map (
      I => xlxn_97(1),
      O => cnt60_t_xlxn_16
    );
  cnt60_t_xlxi_1 : X_AND2
    port map (
      I0 => cnt60_t_xlxn_24,
      I1 => cnt60_t_xlxn_27,
      O => cnt60_t_xlxn_26
    );
  cnt60_t_xlxi_7 : X_AND2
    port map (
      I0 => xlxn_95,
      I1 => cnt60_t_xlxn_8,
      O => cnt60_t_xlxn_27
    );
  cnt60_t_xlxi_6 : X_AND4
    port map (
      I0 => cnt60_t_xlxn_15,
      I1 => xlxn_97(2),
      I2 => cnt60_t_xlxn_16,
      I3 => xlxn_97(0),
      O => cnt60_t_xlxn_24
    );
  decode_t_mrom_one_hot_inst_lut4_91 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => xlxn_35(1),
      ADR1 => xlxn_35(3),
      ADR2 => xlxn_35(0),
      ADR3 => xlxn_35(2),
      O => xlxn_36(9)
    );
  stmach_t_sreg_xx_ffd21 : X_LUT3
    generic map(
      INIT => X"54"
    )
    port map (
      ADR0 => xlxn_5,
      ADR1 => stmach_t_sreg_ffd2,
      ADR2 => stmach_t_sreg_ffd3,
      O => stmach_t_sreg_xx_ffd2
    );
  decode_t_mrom_one_hot_inst_lut4_01 : X_LUT4
    generic map(
      INIT => X"F803"
    )
    port map (
      ADR0 => xlxn_35(0),
      ADR1 => xlxn_35(1),
      ADR2 => xlxn_35(2),
      ADR3 => xlxn_35(3),
      O => xlxn_36(0)
    );
  decode_t_mrom_one_hot_inst_lut4_11 : X_LUT4
    generic map(
      INIT => X"0004"
    )
    port map (
      ADR0 => xlxn_35(0),
      ADR1 => xlxn_35(1),
      ADR2 => xlxn_35(2),
      ADR3 => xlxn_35(3),
      O => xlxn_36(1)
    );
  decode_t_mrom_one_hot_inst_lut4_21 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => xlxn_35(0),
      ADR1 => xlxn_35(1),
      ADR2 => xlxn_35(2),
      ADR3 => xlxn_35(3),
      O => xlxn_36(2)
    );
  decode_t_mrom_one_hot_inst_lut4_31 : X_LUT4
    generic map(
      INIT => X"0004"
    )
    port map (
      ADR0 => xlxn_35(0),
      ADR1 => xlxn_35(2),
      ADR2 => xlxn_35(1),
      ADR3 => xlxn_35(3),
      O => xlxn_36(3)
    );
  decode_t_mrom_one_hot_inst_lut4_41 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => xlxn_35(2),
      ADR1 => xlxn_35(0),
      ADR2 => xlxn_35(1),
      ADR3 => xlxn_35(3),
      O => xlxn_36(4)
    );
  decode_t_mrom_one_hot_inst_lut4_51 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => xlxn_35(2),
      ADR1 => xlxn_35(1),
      ADR2 => xlxn_35(0),
      ADR3 => xlxn_35(3),
      O => xlxn_36(5)
    );
  decode_t_mrom_one_hot_inst_lut4_61 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => xlxn_35(0),
      ADR1 => xlxn_35(1),
      ADR2 => xlxn_35(2),
      ADR3 => xlxn_35(3),
      O => xlxn_36(6)
    );
  decode_t_mrom_one_hot_inst_lut4_71 : X_LUT4
    generic map(
      INIT => X"0004"
    )
    port map (
      ADR0 => xlxn_35(0),
      ADR1 => xlxn_35(3),
      ADR2 => xlxn_35(1),
      ADR3 => xlxn_35(2),
      O => xlxn_36(7)
    );
  hex2led2_mrom_led_inst_lut4_151 : X_LUT4
    generic map(
      INIT => X"208E"
    )
    port map (
      ADR0 => xlxn_97(0),
      ADR1 => xlxn_97(1),
      ADR2 => xlxn_97(2),
      ADR3 => xlxn_97(3),
      O => tensout_5_obuf
    );
  hex2led2_mrom_led_inst_lut4_161 : X_LUT4
    generic map(
      INIT => X"1083"
    )
    port map (
      ADR0 => xlxn_97(0),
      ADR1 => xlxn_97(1),
      ADR2 => xlxn_97(2),
      ADR3 => xlxn_97(3),
      O => tensout_6_obuf
    );
  hex2led2_mrom_led_inst_lut4_101 : X_LUT4
    generic map(
      INIT => X"2812"
    )
    port map (
      ADR0 => xlxn_97(0),
      ADR1 => xlxn_97(1),
      ADR2 => xlxn_97(2),
      ADR3 => xlxn_97(3),
      O => tensout_0_obuf
    );
  hex2led2_mrom_led_inst_lut4_111 : X_LUT4
    generic map(
      INIT => X"D860"
    )
    port map (
      ADR0 => xlxn_97(0),
      ADR1 => xlxn_97(1),
      ADR2 => xlxn_97(2),
      ADR3 => xlxn_97(3),
      O => tensout_1_obuf
    );
  hex2led2_mrom_led_inst_lut4_121 : X_LUT4
    generic map(
      INIT => X"D004"
    )
    port map (
      ADR0 => xlxn_97(0),
      ADR1 => xlxn_97(1),
      ADR2 => xlxn_97(2),
      ADR3 => xlxn_97(3),
      O => tensout_2_obuf
    );
  hex2led2_mrom_led_inst_lut4_131 : X_LUT4