andnor2.sch

用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "virtexe"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        SIGNAL "XLXN_1"
        SIGNAL "XLXN_2"
        SIGNAL "out"
        SIGNAL "in1"
        SIGNAL "in2"
        SIGNAL "in3"
        SIGNAL "in4"
        PORT Output "out"
        PORT Input "in1"
        PORT Input "in2"
        PORT Input "in3"
        PORT Input "in4"
        BEGIN BLOCKDEF "and2"
            TIMESTAMP 2001 2 2 12 25 36
            LINE N 0 -64 64 -64 
            LINE N 0 -128 64 -128 
            LINE N 256 -96 192 -96 
            ARC N 96 -144 192 -48 144 -48 144 -144 
            LINE N 144 -48 64 -48 
            LINE N 64 -144 144 -144 
            LINE N 64 -48 64 -144 
        END BLOCKDEF
        BEGIN BLOCKDEF "nor2"
            TIMESTAMP 2001 2 2 12 25 36
            LINE N 0 -64 64 -64 
            LINE N 0 -128 64 -128 
            LINE N 256 -96 216 -96 
            CIRCLE N 192 -108 216 -84 
            ARC N 28 -224 204 -48 112 -48 192 -96 
            ARC N 28 -144 204 32 192 -96 112 -144 
            ARC N -40 -152 72 -40 48 -48 48 -144 
            LINE N 112 -48 48 -48 
            LINE N 112 -144 48 -144 
        END BLOCKDEF
        BEGIN BLOCK "XLXI_1" "and2"
            PIN "I0" "in2"
            PIN "I1" "in1"
            PIN "O" "XLXN_1"
        END BLOCK
        BEGIN BLOCK "XLXI_2" "and2"
            PIN "I0" "in4"
            PIN "I1" "in3"
            PIN "O" "XLXN_2"
        END BLOCK
        BEGIN BLOCK "XLXI_3" "nor2"
            PIN "I0" "XLXN_2"
            PIN "I1" "XLXN_1"
            PIN "O" "out"
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 3520 2720
        INSTANCE "XLXI_1" 1312 1008 R0
        INSTANCE "XLXI_2" 1312 1152 R0
        INSTANCE "XLXI_3" 1664 1072 R0
        BEGIN BRANCH "XLXN_1"
            WIRE 1568 912 1616 912
            WIRE 1616 912 1616 944
            WIRE 1616 944 1664 944
        END BRANCH
        BEGIN BRANCH "XLXN_2"
            WIRE 1568 1056 1616 1056
            WIRE 1616 1008 1616 1056
            WIRE 1616 1008 1664 1008
        END BRANCH
        BEGIN BRANCH "out"
            WIRE 1920 976 1984 976
        END BRANCH
        BEGIN BRANCH "in1"
            WIRE 1264 880 1312 880
        END BRANCH
        BEGIN BRANCH "in2"
            WIRE 1264 944 1312 944
        END BRANCH
        BEGIN BRANCH "in3"
            WIRE 1264 1024 1312 1024
        END BRANCH
        BEGIN BRANCH "in4"
            WIRE 1264 1088 1296 1088
            WIRE 1296 1088 1312 1088
        END BRANCH
        IOMARKER 1264 880 "in1" R180 28
        IOMARKER 1264 944 "in2" R180 28
        IOMARKER 1264 1024 "in3" R180 28
        IOMARKER 1264 1088 "in4" R180 28
        IOMARKER 1984 976 "out" R0 28
    END SHEET
END SCHEMATIC