isim.hdlsourcefiles

来自「Xilinx DDR2存储器接口调试代码」· HDLSOURCEFILES 代码 · 共 30 行

C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/sim/ddr2_model.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_s3_dq_iob.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_s3_dqs_iob.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_s3_dm_iob_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_wr_gray_cntr.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_fifo_1_wr_en_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_fifo_0_wr_en_0.v
c:/xilinx92/verilog/src/glbl.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_tap_dly.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_cal_ctl_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_cal_top.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_clk_dcm.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_infrastructure_top_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_lfsr32_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_cmp_data_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_cmd_fsm_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_addr_gen_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_test_bench_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_data_path_iobs_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_controller_iobs_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_infrastructure_iobs_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_infrastructure.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_data_write_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_data_read_controller_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_rd_gray_cntr.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_data_read_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_controller_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/rtl/ddr2_32Mx32_top_0.v
C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/sim/sim_tb_top.v