hdpdeps.ref

来自「Xilinx DDR2存储器接口调试代码」· REF 代码 · 共 140 行 · 第 1/2 页

MO isim_temp/ddr2_32Mx32_infrastructure \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_infrastructure.v
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_infrastructure_iobs_0.v 2007/11/27.17:28:00 J.39 FL ../rtl/ddr2_32Mx32_parameters_0.v
MO isim_temp/ddr2_32Mx32_infrastructure_iobs_0 \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_infrastructure_iobs_0.v \
      MI FDDRRSE MI OBUFDS
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_infrastructure_top_0.v 2007/11/27.17:28:00 J.39 FL ../rtl/ddr2_32Mx32_parameters_0.v
MO isim_temp/ddr2_32Mx32_infrastructure_top \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_infrastructure_top_0.v \
      MI IBUFGDS_LVDS_25 MI ddr2_32Mx32_cal_top MI ddr2_32Mx32_clk_dcm
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_iobs_0.v 2007/11/27.17:28:00 J.39 FL ../rtl/ddr2_32Mx32_parameters_0.v
MO isim_temp/ddr2_32Mx32_iobs_0 \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_iobs_0.v \
      MI ddr2_32Mx32_controller_iobs_0 MI ddr2_32Mx32_data_path_iobs_0 \
      MI ddr2_32Mx32_infrastructure_iobs_0
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_lfsr32_0.v 2007/11/27.17:28:00 J.39 FL ../rtl/ddr2_32Mx32_parameters_0.v
MO isim_temp/ddr2_32Mx32_lfsr32_0 \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_lfsr32_0.v
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_main_0.v 2007/11/27.17:28:00 J.39 FL ../rtl/ddr2_32Mx32_parameters_0.v
MO isim_temp/ddr2_32Mx32_main_0 \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_main_0.v \
      MI ddr2_32Mx32_test_bench_0 MI ddr2_32Mx32_top_0
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_ram8d_0.v 2007/11/27.17:28:00 J.39 FL ../rtl/ddr2_32Mx32_parameters_0.v
MO isim_temp/ddr2_32Mx32_ram8d_0 \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_ram8d_0.v \
      MI RAM16X1D
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_rd_gray_cntr.v 2007/11/27.17:28:00 J.39
MO isim_temp/ddr2_32Mx32_rd_gray_cntr \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_rd_gray_cntr.v \
      MI FDRE
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_s3_dm_iob_0.v 2007/11/27.17:28:00 J.39 FL ../rtl/ddr2_32Mx32_parameters_0.v
MO isim_temp/ddr2_32Mx32_s3_dm_iob_0 \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_s3_dm_iob_0.v \
      MI FDDRRSE MI OBUF
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_s3_dqs_iob.v 2007/11/27.17:28:00 J.39
MO isim_temp/ddr2_32Mx32_s3_dqs_iob \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_s3_dqs_iob.v \
      MI FD MI FDDRRSE MI IBUFDS MI OBUFTDS
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_s3_dq_iob.v 2007/11/27.17:28:00 J.39
MO isim_temp/ddr2_32Mx32_s3_dq_iob \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_s3_dq_iob.v \
      MI FD MI FDDRRSE MI IBUF MI OBUFT
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_tap_dly.v 2007/11/27.17:28:00 J.39
MO isim_temp/ddr2_32Mx32_tap_dly \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_tap_dly.v \
      MI FDR MI LUT4
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_test_bench_0.v 2007/11/27.17:28:00 J.39 FL ../rtl/ddr2_32Mx32_parameters_0.v
MO isim_temp/ddr2_32Mx32_test_bench_0 \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_test_bench_0.v \
      MI ddr2_32Mx32_addr_gen_0 MI ddr2_32Mx32_cmd_fsm_0 MI ddr2_32Mx32_cmp_data_0 \
      MI ddr2_32Mx32_lfsr32_0
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_top_0.v 2007/11/27.17:28:00 J.39 FL ../rtl/ddr2_32Mx32_parameters_0.v
MO isim_temp/ddr2_32Mx32_top_0 \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_top_0.v \
      MI ddr2_32Mx32_controller_0 MI ddr2_32Mx32_data_path_0 \
      MI ddr2_32Mx32_infrastructure MI ddr2_32Mx32_iobs_0
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_wr_gray_cntr.v 2007/11/27.17:28:00 J.39
MO isim_temp/ddr2_32Mx32_wr_gray_cntr \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_wr_gray_cntr.v \
      MI FDCE
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../sim/ddr2_model.v 2007/12/19.11:00:56 J.39 FL ../sim/ddr2_model_parameters.vh
MO isim_temp/ddr2_model \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../sim/ddr2_model.v
FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../sim/sim_tb_top.v 2007/12/19.11:15:33 J.39 FL ../rtl/ddr2_32Mx32_parameters_0.v
MO isim_temp/sim_tb_top \
      FL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../sim/sim_tb_top.v \
      MI ddr2_32Mx32 MI ddr2_model
FL $XILINX/verilog/src/glbl.v 2007/05/18.14:22:56 J.39
MO isim_temp/glbl FL $XILINX/verilog/src/glbl.v