hdllib.ref

来自「Xilinx DDR2存储器接口调试代码」· REF 代码 · 共 36 行

MO ddr2_32Mx32_cmp_data_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_cmp_data_0.v vlg2D/ddr2__32_mx32__cmp__data__0.bin 1198088832
MO ddr2_32Mx32_cal_ctl NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_cal_ctl_0.v vlg1B/ddr2__32_mx32__cal__ctl.bin 1198088832
MO ddr2_32Mx32_top_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_top_0.v vlg2B/ddr2__32_mx32__top__0.bin 1198088832
MO ddr2_32Mx32_data_read_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_data_read_0.v vlg4D/ddr2__32_mx32__data__read__0.bin 1198088831
MO ddr2_32Mx32_cmd_fsm_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_cmd_fsm_0.v vlg71/ddr2__32_mx32__cmd__fsm__0.bin 1198088832
MO ddr2_32Mx32_cal_top NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_cal_top.v vlg2F/ddr2__32_mx32__cal__top.bin 1198088832
MO ddr2_32Mx32_data_read_controller_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_data_read_controller_0.v vlg48/ddr2__32_mx32__data__read__controller__0.bin 1198088831
MO ddr2_32Mx32_tap_dly NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_tap_dly.v vlg76/ddr2__32_mx32__tap__dly.bin 1198088831
MO ddr2_32Mx32_fifo_1_wr_en_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_fifo_1_wr_en_0.v vlg7A/ddr2__32_mx32__fifo__1__wr__en__0.bin 1198088831
MO ddr2_32Mx32_fifo_0_wr_en_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_fifo_0_wr_en_0.v vlg19/ddr2__32_mx32__fifo__0__wr__en__0.bin 1198088831
MO ddr2_32Mx32_dqs_delay NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_dqs_delay.v vlg0F/ddr2__32_mx32__dqs__delay.bin 1198088831
MO sim_tb_top NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../sim/sim_tb_top.v vlg40/sim__tb__top.bin 1198088833
MO ddr2_32Mx32_s3_dqs_iob NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_s3_dqs_iob.v vlg5F/ddr2__32_mx32__s3__dqs__iob.bin 1198088831
MO ddr2_32Mx32_data_write_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_data_write_0.v vlg68/ddr2__32_mx32__data__write__0.bin 1198088831
MO ddr2_32Mx32_iobs_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_iobs_0.v vlg49/ddr2__32_mx32__iobs__0.bin 1198088832
MO ddr2_32Mx32_wr_gray_cntr NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_wr_gray_cntr.v vlg2E/ddr2__32_mx32__wr__gray__cntr.bin 1198088831
MO ddr2_32Mx32 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32.v vlg2E/ddr2__32_mx32.bin 1198088833
MO ddr2_32Mx32_s3_dm_iob_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_s3_dm_iob_0.v vlg47/ddr2__32_mx32__s3__dm__iob__0.bin 1198088831
MO ddr2_32Mx32_s3_dq_iob NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_s3_dq_iob.v vlg60/ddr2__32_mx32__s3__dq__iob.bin 1198088831
MO ddr2_32Mx32_data_path_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_data_path_0.v vlg4A/ddr2__32_mx32__data__path__0.bin 1198088832
MO ddr2_32Mx32_lfsr32_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_lfsr32_0.v vlg2C/ddr2__32_mx32__lfsr32__0.bin 1198088832
MO ddr2_32Mx32_clk_dcm NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_clk_dcm.v vlg36/ddr2__32_mx32__clk__dcm.bin 1198088832
MO ddr2_32Mx32_controller_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_controller_0.v vlg14/ddr2__32_mx32__controller__0.bin 1198088832
MO ddr2_32Mx32_ram8d_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_ram8d_0.v vlg7C/ddr2__32_mx32__ram8d__0.bin 1198088831
MO ddr2_32Mx32_infrastructure NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_infrastructure.v vlg02/ddr2__32_mx32__infrastructure.bin 1198088832
MO ddr2_32Mx32_test_bench_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_test_bench_0.v vlg2F/ddr2__32_mx32__test__bench__0.bin 1198088832
MO ddr2_model NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../sim/ddr2_model.v vlg48/ddr2__model.bin 1198088833
MO ddr2_32Mx32_main_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_main_0.v vlg5D/ddr2__32_mx32__main__0.bin 1198088832
MO glbl NULL c:/xilinx92/verilog/src/glbl.v vlg2D/glbl.bin 1198088833
MO ddr2_32Mx32_rd_gray_cntr NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_rd_gray_cntr.v vlg3F/ddr2__32_mx32__rd__gray__cntr.bin 1198088831
MO ddr2_32Mx32_controller_iobs_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_controller_iobs_0.v vlg10/ddr2__32_mx32__controller__iobs__0.bin 1198088831
MO ddr2_32Mx32_infrastructure_iobs_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_infrastructure_iobs_0.v vlg0D/ddr2__32_mx32__infrastructure__iobs__0.bin 1198088831
MO ddr2_32Mx32_addr_gen_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_addr_gen_0.v vlg18/ddr2__32_mx32__addr__gen__0.bin 1198088832
MO ddr2_32Mx32_data_path_iobs_0 NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_data_path_iobs_0.v vlg3E/ddr2__32_mx32__data__path__iobs__0.bin 1198088831
MO ddr2_32Mx32_infrastructure_top NULL C:/Work/tutorials/Xilinx/3s1800ad_Starter/Xil3SD1800A_MIG_ISIM_vlog_v92/ddr2_32Mx32_vlog/ddr2_32Mx32/example_design/par/../rtl/ddr2_32Mx32_infrastructure_top_0.v vlg34/ddr2__32_mx32__infrastructure__top.bin 1198088833