hdllib.ref

来自「Xilinx DDR2存储器接口调试代码」· REF 代码 · 共 20 行

MO IBUFDS NULL N:/J.39/rtf/verilog/src/unisims/IBUFDS.v vlg.bin:9423462 1188404617
MO OBUFTDS NULL N:/J.39/rtf/verilog/src/unisims/OBUFTDS.v vlg.bin:9851992 1188404871
MO FD NULL N:/J.39/rtf/verilog/src/unisims/FD.v vlg.bin:8947298 1188404596
MO OBUFDS NULL N:/J.39/rtf/verilog/src/unisims/OBUFDS.v vlg.bin:9832688 1188404857
MO FDCE NULL N:/J.39/rtf/verilog/src/unisims/FDCE.v vlg.bin:8952356 1188404598
MO FDR NULL N:/J.39/rtf/verilog/src/unisims/FDR.v vlg.bin:48231 1188404238
MO OBUF NULL N:/J.39/rtf/verilog/src/unisims/OBUF.v vlg.bin:9830614 1188404856
MO IBUF NULL N:/J.39/rtf/verilog/src/unisims/IBUF.v vlg.bin:9419880 1188404617
MO dcm_maximum_period_check NULL N:/J.39/rtf/verilog/src/unisims/DCM.v vlg.bin:8827507 1188404594
MO IBUFGDS_LVDS_25 NULL N:/J.39/rtf/verilog/src/unisims/IBUFGDS_LVDS_25.v vlg.bin:9477051 1188404640
MO FDDRRSE NULL N:/J.39/rtf/verilog/src/unisims/FDDRRSE.v vlg.bin:22245 1188404238
MO FDRE NULL N:/J.39/rtf/verilog/src/unisims/FDRE.v vlg.bin:51106 1188404238
MO dcm_clock_divide_by_2 NULL N:/J.39/rtf/verilog/src/unisims/DCM.v vlg.bin:8823725 1188404594
MO LUT4 NULL N:/J.39/rtf/verilog/src/unisims/LUT4.v vlg.bin:1491858 1188404301
MO RAM16X1D NULL N:/J.39/rtf/verilog/src/unisims/RAM16X1D.v vlg.bin:1911566 1188404428
MO dcm_clock_lost NULL N:/J.39/rtf/verilog/src/unisims/DCM.v vlg.bin:8829455 1188404594
MO OBUFT NULL N:/J.39/rtf/verilog/src/unisims/OBUFT.v vlg.bin:9849388 1188404869
MO BUFGMUX NULL N:/J.39/rtf/verilog/src/unisims/BUFGMUX.v vlg.bin:8583142 1188404578
MO DCM NULL N:/J.39/rtf/verilog/src/unisims/DCM.v vlg.bin:8736119 1188404594