xsimsimtbtop.cpp

来自「Xilinx DDR2存储器接口调试代码」· C++ 代码 · 共 892 行 · 第 1/2 页
CPP
892 行
}


static HSim__s6* IF49(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_b_u_f_g_m_u_x(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_b_u_f_g_m_u_x(label); 
    return blk;
}


static HSim__s6* IF50(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_d_c_m(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_d_c_m(label); 
    return blk;
}


static HSim__s6* IF51(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_d_c_m(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_d_c_m(label); 
    return blk;
}


static HSim__s6* IF52(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_d_c_m(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_d_c_m(label); 
    return blk;
}


static HSim__s6* IF53(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_d_c_m(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_d_c_m(label); 
    return blk;
}


static HSim__s6* IF54(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_f_d(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_f_d(label); 
    return blk;
}


static HSim__s6* IF55(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__data__write__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__data__write__0(label); 
    return blk;
}


static HSim__s6* IF56(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__data__read__controller__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__data__read__controller__0(label); 
    return blk;
}


static HSim__s6* IF57(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__data__read__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__data__read__0(label); 
    return blk;
}


static HSim__s6* IF58(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__infrastructure__iobs__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__infrastructure__iobs__0(label); 
    return blk;
}


static HSim__s6* IF59(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__data__path__iobs__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__data__path__iobs__0(label); 
    return blk;
}


static HSim__s6* IF60(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__controller__iobs__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__controller__iobs__0(label); 
    return blk;
}


static HSim__s6* IF61(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_i_b_u_f_g_d_s___l_v_d_s__25(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_i_b_u_f_g_d_s___l_v_d_s__25(label); 
    return blk;
}


static HSim__s6* IF62(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__tap__dly(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__tap__dly(label); 
    return blk;
}


static HSim__s6* IF63(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__cal__ctl(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__cal__ctl(label); 
    return blk;
}


static HSim__s6* IF64(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_d_c_m(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_d_c_m(label); 
    return blk;
}


static HSim__s6* IF65(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_b_u_f_g_m_u_x(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_b_u_f_g_m_u_x(label); 
    return blk;
}


static HSim__s6* IF66(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__lfsr32__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__lfsr32__0(label); 
    return blk;
}


static HSim__s6* IF67(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__cmp__data__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__cmp__data__0(label); 
    return blk;
}


static HSim__s6* IF68(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__cmd__fsm__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__cmd__fsm__0(label); 
    return blk;
}


static HSim__s6* IF69(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__addr__gen__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__addr__gen__0(label); 
    return blk;
}


static HSim__s6* IF70(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__iobs__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__iobs__0(label); 
    return blk;
}


static HSim__s6* IF71(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__infrastructure(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__infrastructure(label); 
    return blk;
}


static HSim__s6* IF72(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__data__path__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__data__path__0(label); 
    return blk;
}


static HSim__s6* IF73(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__controller__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__controller__0(label); 
    return blk;
}


static HSim__s6* IF74(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__clk__dcm(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__clk__dcm(label); 
    return blk;
}


static HSim__s6* IF75(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__cal__top(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__cal__top(label); 
    return blk;
}


static HSim__s6* IF76(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createunisim_ver_auxlibM_i_b_u_f_g_d_s___l_v_d_s__25(const char*);
    HSim__s6 *blk = createunisim_ver_auxlibM_i_b_u_f_g_d_s___l_v_d_s__25(label); 
    return blk;
}


static HSim__s6* IF77(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__top__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__top__0(label); 
    return blk;
}


static HSim__s6* IF78(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__test__bench__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__test__bench__0(label); 
    return blk;
}


static HSim__s6* IF79(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__main__0(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__main__0(label); 
    return blk;
}


static HSim__s6* IF80(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32__infrastructure__top(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32__infrastructure__top(label); 
    return blk;
}


static HSim__s6* IF81(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__model(const char*);
    HSim__s6 *blk = createworkMddr2__model(label); 
    return blk;
}


static HSim__s6* IF82(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMddr2__32_mx32(const char*);
    HSim__s6 *blk = createworkMddr2__32_mx32(label); 
    return blk;
}


static HSim__s6* IF83(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    extern HSim__s6 * createworkMglbl(const char*);
    HSim__s6 *blk = createworkMglbl(label); 
    return blk;
}

class _top : public HSim__s6 {
public:
    _top() : HSim__s6(false, "_top", "_top", 0, 0, HSim::VerilogModule) {}
    HSimConfigDecl * topModuleInstantiate() {
        HSimConfigDecl * cfgvh = 0;
        cfgvh = new HSimConfigDecl("default");
        (*cfgvh).registerFuseLibList("unisims_ver;xilinxcorelib_ver");

        (*cfgvh).addVlogModule("work","sim_tb_top", (HSimInstFactoryPtr)IF0);
        (*cfgvh).addVlogModule("unisims_ver","RAM16X1D", (HSimInstFactoryPtr)IF1);
        (*cfgvh).addVlogModule("unisims_ver","FDRE", (HSimInstFactoryPtr)IF2);
        (*cfgvh).addVlogModule("unisims_ver","LUT4", (HSimInstFactoryPtr)IF3);
        (*cfgvh).addVlogModule("unisims_ver","FDCE", (HSimInstFactoryPtr)IF4);
        (*cfgvh).addVlogModule("unisims_ver","FDDRRSE", (HSimInstFactoryPtr)IF5);
        (*cfgvh).addVlogModule("unisims_ver","OBUF", (HSimInstFactoryPtr)IF6);
        (*cfgvh).addVlogModule("unisims_ver","FD", (HSimInstFactoryPtr)IF7);
        (*cfgvh).addVlogModule("unisims_ver","IBUF", (HSimInstFactoryPtr)IF8);
        (*cfgvh).addVlogModule("unisims_ver","OBUFT", (HSimInstFactoryPtr)IF9);
        (*cfgvh).addVlogModule("unisims_ver","IBUFDS", (HSimInstFactoryPtr)IF10);
        (*cfgvh).addVlogModule("unisims_ver","OBUFTDS", (HSimInstFactoryPtr)IF11);
        (*cfgvh).addVlogModule("unisims_ver","RAM16X1D", (HSimInstFactoryPtr)IF12);
        (*cfgvh).addVlogModule("unisims_ver","FDRE", (HSimInstFactoryPtr)IF13);
        (*cfgvh).addVlogModule("unisims_ver","LUT4", (HSimInstFactoryPtr)IF14);
        (*cfgvh).addVlogModule("unisims_ver","FDCE", (HSimInstFactoryPtr)IF15);
        (*cfgvh).addVlogModule("unisims_ver","FDCE", (HSimInstFactoryPtr)IF16);
        (*cfgvh).addVlogModule("unisims_ver","FDCE", (HSimInstFactoryPtr)IF17);
        (*cfgvh).addVlogModule("unisims_ver","OBUF", (HSimInstFactoryPtr)IF18);
        (*cfgvh).addVlogModule("unisims_ver","FDDRRSE", (HSimInstFactoryPtr)IF19);
        (*cfgvh).addVlogModule("unisims_ver","OBUFT", (HSimInstFactoryPtr)IF20);
        (*cfgvh).addVlogModule("unisims_ver","IBUF", (HSimInstFactoryPtr)IF21);
        (*cfgvh).addVlogModule("unisims_ver","FDDRRSE", (HSimInstFactoryPtr)IF22);
        (*cfgvh).addVlogModule("unisims_ver","FD", (HSimInstFactoryPtr)IF23);
        (*cfgvh).addVlogModule("unisims_ver","OBUFTDS", (HSimInstFactoryPtr)IF24);
        (*cfgvh).addVlogModule("unisims_ver","IBUFDS", (HSimInstFactoryPtr)IF25);
        (*cfgvh).addVlogModule("unisims_ver","FDDRRSE", (HSimInstFactoryPtr)IF26);
        (*cfgvh).addVlogModule("unisims_ver","FD", (HSimInstFactoryPtr)IF27);
        (*cfgvh).addVlogModule("unisims_ver","OBUFDS", (HSimInstFactoryPtr)IF28);
        (*cfgvh).addVlogModule("unisims_ver","FDR", (HSimInstFactoryPtr)IF29);
        (*cfgvh).addVlogModule("unisims_ver","dcm_clock_divide_by_2", (HSimInstFactoryPtr)IF30);
        (*cfgvh).addVlogModule("unisims_ver","dcm_clock_lost", (HSimInstFactoryPtr)IF31);
        (*cfgvh).addVlogModule("unisims_ver","dcm_maximum_period_check", (HSimInstFactoryPtr)IF32);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_rd_gray_cntr", (HSimInstFactoryPtr)IF33);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_ram8d_0", (HSimInstFactoryPtr)IF34);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_wr_gray_cntr", (HSimInstFactoryPtr)IF35);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_fifo_1_wr_en_0", (HSimInstFactoryPtr)IF36);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_fifo_0_wr_en_0", (HSimInstFactoryPtr)IF37);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_dqs_delay", (HSimInstFactoryPtr)IF38);
        (*cfgvh).addVlogModule("unisims_ver","OBUF", (HSimInstFactoryPtr)IF39);
        (*cfgvh).addVlogModule("unisims_ver","IBUF", (HSimInstFactoryPtr)IF40);
        (*cfgvh).addVlogModule("unisims_ver","FD", (HSimInstFactoryPtr)IF41);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_s3_dqs_iob", (HSimInstFactoryPtr)IF42);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_s3_dq_iob", (HSimInstFactoryPtr)IF43);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_s3_dm_iob_0", (HSimInstFactoryPtr)IF44);
        (*cfgvh).addVlogModule("unisims_ver","OBUFDS", (HSimInstFactoryPtr)IF45);
        (*cfgvh).addVlogModule("unisims_ver","FDDRRSE", (HSimInstFactoryPtr)IF46);
        (*cfgvh).addVlogModule("unisims_ver","LUT4", (HSimInstFactoryPtr)IF47);
        (*cfgvh).addVlogModule("unisims_ver","FDR", (HSimInstFactoryPtr)IF48);
        (*cfgvh).addVlogModule("unisims_ver","BUFGMUX", (HSimInstFactoryPtr)IF49);
        (*cfgvh).addVlogModule("unisims_ver","DCM", (HSimInstFactoryPtr)IF50);
        (*cfgvh).addVlogModule("unisims_ver","DCM", (HSimInstFactoryPtr)IF51);
        (*cfgvh).addVlogModule("unisims_ver","DCM", (HSimInstFactoryPtr)IF52);
        (*cfgvh).addVlogModule("unisims_ver","DCM", (HSimInstFactoryPtr)IF53);
        (*cfgvh).addVlogModule("unisims_ver","FD", (HSimInstFactoryPtr)IF54);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_data_write_0", (HSimInstFactoryPtr)IF55);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_data_read_controller_0", (HSimInstFactoryPtr)IF56);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_data_read_0", (HSimInstFactoryPtr)IF57);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_infrastructure_iobs_0", (HSimInstFactoryPtr)IF58);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_data_path_iobs_0", (HSimInstFactoryPtr)IF59);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_controller_iobs_0", (HSimInstFactoryPtr)IF60);
        (*cfgvh).addVlogModule("unisims_ver","IBUFGDS_LVDS_25", (HSimInstFactoryPtr)IF61);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_tap_dly", (HSimInstFactoryPtr)IF62);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_cal_ctl", (HSimInstFactoryPtr)IF63);
        (*cfgvh).addVlogModule("unisims_ver","DCM", (HSimInstFactoryPtr)IF64);
        (*cfgvh).addVlogModule("unisims_ver","BUFGMUX", (HSimInstFactoryPtr)IF65);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_lfsr32_0", (HSimInstFactoryPtr)IF66);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_cmp_data_0", (HSimInstFactoryPtr)IF67);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_cmd_fsm_0", (HSimInstFactoryPtr)IF68);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_addr_gen_0", (HSimInstFactoryPtr)IF69);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_iobs_0", (HSimInstFactoryPtr)IF70);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_infrastructure", (HSimInstFactoryPtr)IF71);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_data_path_0", (HSimInstFactoryPtr)IF72);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_controller_0", (HSimInstFactoryPtr)IF73);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_clk_dcm", (HSimInstFactoryPtr)IF74);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_cal_top", (HSimInstFactoryPtr)IF75);
        (*cfgvh).addVlogModule("unisims_ver","IBUFGDS_LVDS_25", (HSimInstFactoryPtr)IF76);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_top_0", (HSimInstFactoryPtr)IF77);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_test_bench_0", (HSimInstFactoryPtr)IF78);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_main_0", (HSimInstFactoryPtr)IF79);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32_infrastructure_top", (HSimInstFactoryPtr)IF80);
        (*cfgvh).addVlogModule("work","ddr2_model", (HSimInstFactoryPtr)IF81);
        (*cfgvh).addVlogModule("work","ddr2_32Mx32", (HSimInstFactoryPtr)IF82);
        (*cfgvh).addVlogModule("work","glbl", (HSimInstFactoryPtr)IF83);
        HSim__s5 * topvl = 0;
        extern HSim__s6 * createworkMsim__tb__top(const char*);
        topvl = (HSim__s5*)createworkMsim__tb__top("sim_tb_top");
        topvl->moduleInstantiate(cfgvh);
        addChild(topvl);
        extern HSim__s6 * createworkMglbl(const char*);
        topvl = (HSim__s5*)createworkMglbl("glbl");
        topvl->moduleInstantiate(cfgvh);
        addChild(topvl);
        return cfgvh;
}
};

main(int argc, char **argv) {
  HSimDesign::initDesign();
  globalKernel->getOptions(argc,argv);
  HSim__s6 * _top_i = 0;
  try {
    HSimConfigDecl *cfg;
 _top_i = new _top();
  cfg =  _top_i->topModuleInstantiate();
    return globalKernel->runTcl(cfg, _top_i, "_top", argc, argv);
  }
  catch (HSimError& msg){
    try {
      globalKernel->error(msg.ErrMsg);
      return 1;
    }
    catch(...) {}
      return 1;
  }
  catch (...){
    globalKernel->fatalError();
    return 1;
  }
}
xsimsimtbtop.cpp - 源码说明

本页面展示了「Xilinx DDR2存储器接口调试代码」中的 xsimsim__tb__top.cpp 源码文件，采用 C++ 编程语言编写，共 892 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
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xsimsim__tb__top.cpp

xsimsim__tb__top.cpp - 源码说明

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xsimsimtbtop.cpp

xsimsimtbtop.cpp - 源码说明
