datasheet.txt

Xilinx DDR2存储器接口调试代码

                            Datasheet  
Generated by mig Version 2.0 on Tue November 27 17:28 2007

*************   INPUTS GIVEN   ***********
 PART                     : xc3sd1800afg676
 Frequency in MHz         : 125
 Speed grade              : -4
 No of controllers        : 1
 Synthesis tool           : XST 
 HDL                      : verilog
 Implementation Options:           
 DCM used                 : 1        
 Add test bench           : 1         
 Number of write pipelines: 4         

**************************************
 Generating interface for controller 0
 Memory type              : DDR2_SDRAM/Components/MT47H32M16XX-5E 
 Bits per strobe          : X8
 Banks for Data           : 3
 Data bits                : 32
 Banks for addr & cntrl   : 3
 Banks for System Control : 3
 Banks for System Clock   : 0
 Row address bits         : 13
 Column address bits      : 10
 Bank address bits        : 2
****************************************************
Design Parameters : 
       Mode Register : 
            Burst Length                : 8(011)
            Burst Type                  : sequential(0)
            CAS Latency                 : 3(011)
            Mode                        : normal(0)
            DLL Reset                   : yes(1)
            PD Mode                     : fast exit(0)
            Write Recovery              : 3(010)
       Extended Mode Register : 
            DLL Enable                  : Enable-Normal(0)
            Output Drive Strength       : Fullstrength(0)
            RTT (nominal) - ODT         : 50ohms(11)
            Additive Latency (AL)       : 0(000)
            OCD Operation               : OCD Exit(000)
            DQS# Enable                 : Enable(0)
            RDQS Enable                 : Disable(0)
            Outputs                     : Enable(0)