ddr2_32mx32_infrastructure.v

来自「Xilinx DDR2存储器接口调试代码」· Verilog 代码 · 共 50 行

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_infrastructure.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:18 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	:
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
module ddr2_32Mx32_infrastructure
  (
   input        clk_int,
   input        rst_calib1,
   input [4:0]  delay_sel_val,
   output [4:0] delay_sel_val1_val
   );


   reg [4:0] delay_sel_val1; 
   reg       rst_calib1_r1;
   reg       rst_calib1_r2;


   assign delay_sel_val1_val = delay_sel_val1;

   always@(negedge clk_int) 
     rst_calib1_r1    <= rst_calib1;

   always@(posedge clk_int) 
     rst_calib1_r2    <= rst_calib1_r1;
   
   always@(posedge clk_int) begin
      if( rst_calib1_r2 == 1'b0 )
	delay_sel_val1    <= delay_sel_val;
      else
	delay_sel_val1      <= delay_sel_val1;
   end

endmodule