ddr2_32mx32_fifo_1_wr_en_0.v

来自「Xilinx DDR2存储器接口调试代码」· Verilog 代码 · 共 50 行

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This	design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /	/\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \	\        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_fifo_1_wr_en_0.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:18 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module generate the write enable signal to the fifos, 
//		  which are driven by posedge data strobe.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
module ddr2_32Mx32_fifo_1_wr_en_0
  (
   input  clk,
   input  rst_dqs_delay_n,
   input  reset,
   input  din,
   output dout
   );

   localparam TIE_HIGH = 1'b1;

   wire din_delay;
   wire dout0;
   wire rst_dqs_delay;

   assign rst_dqs_delay = ~rst_dqs_delay_n;
   assign dout0         = din & rst_dqs_delay_n;
   assign dout          = rst_dqs_delay | din_delay;

   FDCE	delay_ff_1
     (
      .Q   (din_delay), 
      .C   (clk), 
      .CE  (TIE_HIGH), 
      .CLR (reset), 
      .D   (dout0)
      );

endmodule