ddr2_32mx32_main_0.v

来自「Xilinx DDR2存储器接口调试代码」· Verilog 代码 · 共 131 行

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_main_0.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:18 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This modules has the instantiation for top and test_bench 
//		  modules.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
`include "../rtl/ddr2_32Mx32_parameters_0.v"

module    ddr2_32Mx32_main_0
  (
   input                            clk_int,
   input                            clk90_int,
   input [4:0]                      delay_sel_val,
   input                            sys_rst,
   input                            sys_rst90,
   input                            sys_rst180,
   input                            rst_dqs_div_in,
   output                           rst_dqs_div_out,
   output [(`CLK_WIDTH-1):0]        ddr2_ck,
   output [(`CLK_WIDTH-1):0]        ddr2_ck_n,
   output                           ddr2_cas_n,
   output                           ddr2_cke,
   output                           ddr2_cs_n,
   output                           ddr2_ras_n,
   output                           ddr2_we_n,
   output                           ddr2_odt,
   output [`ROW_ADDRESS-1:0]        ddr2_a,
   output [`BANK_ADDRESS-1:0]       ddr2_ba,
   inout [(`DATA_WIDTH-1):0]        ddr2_dq,
   input                            wait_200us,
   inout [(`DATA_STROBE_WIDTH-1):0] ddr2_dqs,
   output       [((`DATA_MASK_WIDTH)-1):0]  ddr2_dm,
    inout  [(`DATA_STROBE_WIDTH-1):0] ddr2_dqs_n, 

   output                           init_done,
   output                           led_error_output1,
   output                           data_valid_out

   );


   wire [((`DATA_WIDTH*2)-1):0]                  user_output_data;
   wire [((`ROW_ADDRESS +
           `COL_AP_WIDTH  + `BANK_ADDRESS)-1):0] u1_address;
   wire                                          user_data_val1;
   wire [2:0]                                    user_cmd1;
   wire                                          auto_ref_req;
   wire                                          user_ack1;
   wire [((`DATA_WIDTH*2)-1):0]                  u1_data_i;
   wire [((`DATA_MASK_WIDTH*2)-1):0]             u1_data_m;
   wire                                          burst_done_val1;
   wire                                          ar_done_val1;


   ddr2_32Mx32_top_0        top0
      (
       .auto_ref_req		(auto_ref_req),
       .wait_200us		(wait_200us),
       .rst_dqs_div_in		(rst_dqs_div_in),
       .rst_dqs_div_out		(rst_dqs_div_out),
       .user_input_data		(u1_data_i),
      .user_data_mask(u1_data_m),
       .user_output_data	(user_output_data),
       .user_data_valid		(user_data_val1),
       .user_input_address	(u1_address[((`ROW_ADDRESS + `COL_AP_WIDTH 
                                            + `BANK_ADDRESS)-1):0]),
       .user_command_register   (user_cmd1),
       .user_cmd_ack		(user_ack1),
       .burst_done		(burst_done_val1),
       .init_done		(init_done),
       .ar_done			(ar_done_val1),
       .ddr2_dqs		(ddr2_dqs),
      .ddr2_dqs_n (ddr2_dqs_n),
       .ddr2_dq			(ddr2_dq),
       .ddr2_cke		(ddr2_cke),
       .ddr2_cs_n		(ddr2_cs_n),
       .ddr2_ras_n		(ddr2_ras_n),
       .ddr2_cas_n		(ddr2_cas_n),
       .ddr2_we_n		(ddr2_we_n),
      .ddr2_dm          (ddr2_dm),

       .ddr2_odt		(ddr2_odt),
       .ddr2_ba			(ddr2_ba),
       .ddr2_a			(ddr2_a),
       .ddr2_ck			(ddr2_ck),
       .ddr2_ck_n		(ddr2_ck_n),
       .clk_int			(clk_int),
       .clk90_int		(clk90_int),
       .delay_sel_val		(delay_sel_val),
       .sys_rst			(sys_rst),
       .sys_rst90		(sys_rst90),
       .sys_rst180		(sys_rst180)
       );

   ddr2_32Mx32_test_bench_0    test_bench0
      (
       .auto_ref_req      (auto_ref_req),
       .fpga_clk          (clk_int),
       .fpga_rst90        (sys_rst90),
       .fpga_rst180       (sys_rst180),
       .clk90             (clk90_int),
       .burst_done        (burst_done_val1),
       .init_done         (init_done),
       .ar_done           (ar_done_val1),
       .u_ack             (user_ack1),
       .u_data_val        (user_data_val1),
       .u_data_o          (user_output_data),
       .u_addr            (u1_address),
       .u_cmd             (user_cmd1),
       .u_data_i          (u1_data_i),
       .u_data_m          (u1_data_m),
       .led_error_output  (led_error_output1),
       .data_valid_out    (data_valid_out)
       );

endmodule