ddr2_32mx32_test_bench_0.v

来自「Xilinx DDR2存储器接口调试代码」· Verilog 代码 · 共 223 行

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_test_bench_0.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:18 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module generate the commands, address and data associated
//                 with a write and a read command.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
`include "../rtl/ddr2_32Mx32_parameters_0.v"

module    ddr2_32Mx32_test_bench_0
  (
   input                                          fpga_clk,
   input                                          fpga_rst90,
   input                                          fpga_rst180,
   input                                          clk90,
   input                                          init_done,
   input                                          ar_done,
   input                                          u_ack,
   input                                          u_data_val,
   input [(2*`DATA_WIDTH)-1:0]                    u_data_o,
   input                                          auto_ref_req,
   output                                         burst_done,
   output [((`ROW_ADDRESS +
             `COL_AP_WIDTH + `BANK_ADDRESS)-1):0] u_addr,
   output [2:0]                                   u_cmd,
   output [(2*`DATA_WIDTH)-1:0]                   u_data_i,
   output [((`DATA_MASK_WIDTH*2)-1):0]            u_data_m,
   output                                         led_error_output,
   output                                         data_valid_out
   );

   wire                                         clk;
   wire                                         addr_inc;
   wire                                         addr_rst;
   wire                                         cmd_ack;
   wire                                         cnt_roll;
   wire                                         data_valid;
   wire                                         lfsr_rst_r1;
   wire                                         lfsr_rst_w;
   wire                                         r_w;
   wire [(2*`DATA_WIDTH)-1:0]                   lfsr_data_w0;
   wire [(2*`DATA_WIDTH)-1:0]                   lfsr_data_r;
   wire [((`DATA_MASK_WIDTH*2)-1):0]            lfsr_data_m_r;
   wire [((`DATA_MASK_WIDTH*2)-1):0]            lfsr_data_m_w0;
   wire [((`ROW_ADDRESS + 
           `COL_AP_WIDTH + `BANK_ADDRESS)-1):0] addr_out;
   wire                                         u_dat_fl;

   reg [(2*`DATA_WIDTH)-1:0]                    lfsr_data_w1;
   reg [(2*`DATA_WIDTH)-1:0]                    lfsr_data_w2;
   reg [(2*`DATA_WIDTH)-1:0]                    lfsr_data_w3;
   reg [(2*`DATA_WIDTH)-1:0]                    lfsr_data_w4;
   reg [(`DATA_MASK_WIDTH*2)-1:0]               lfsr_data_m_w1;
   reg [(`DATA_MASK_WIDTH*2)-1:0]               lfsr_data_m_w2;
   reg [(`DATA_MASK_WIDTH*2)-1:0]               lfsr_data_m_w3;
   reg [(`DATA_MASK_WIDTH*2)-1:0]               lfsr_data_m_w4;
   reg                                          rst90_r;
   reg                                          lfsr_ena_r;
   reg                                          lfsr_ena_w;
   reg                                          u_dat_flag;
   reg                                          lfsr_rst_r;

   

// Output : COMMAND REGISTER FORMAT
//          000  - NOP
//          010  - Initialize memory
//          100  - Write Request
//          110  - Read request

// Output : Address format
//   row address    = address((`ROW_ADDRESS + `COL_AP_WIDTH + `BANK_ADDRESS) -1 
//					  : (`COL_AP_WIDTH + `BANK_ADDRESS))
//   column address = address((`COL_AP_WIDTH + `BANK_ADDRESS)-1 : `BANK_ADDRESS)
//   Bank address     = address(`BANK_ADDRESS - 1 : 0)

   assign clk        = fpga_clk;
   assign cmd_ack    = u_ack;
   assign data_valid = u_data_val;
   assign u_addr     = addr_out;

     
         assign                         u_data_i       = lfsr_data_w0;
   assign                         u_data_m       = lfsr_data_m_w0;


   always @ (posedge clk90) 
      rst90_r <= fpga_rst90;

   always @ (posedge clk90) begin
      if (rst90_r == 1'b1) begin
         lfsr_data_w1 <= 'b0;        
         lfsr_data_w2 <= 'b0;
         lfsr_data_w3 <= 'b0;
         lfsr_data_w4 <= 'b0;
         lfsr_data_m_w1 <= 'b0;        
         lfsr_data_m_w2 <= 'b0;
         lfsr_data_m_w3 <= 'b0;
         lfsr_data_m_w4 <= 'b0;
      end
      else begin
         lfsr_data_w1 <= lfsr_data_w0;        
         lfsr_data_w2 <= lfsr_data_w1;
         lfsr_data_w3 <= lfsr_data_w2;
         lfsr_data_w4 <= lfsr_data_w3;
         lfsr_data_m_w1 <= lfsr_data_m_w0;        
         lfsr_data_m_w2 <= lfsr_data_m_w1;
         lfsr_data_m_w3 <= lfsr_data_m_w2;
         lfsr_data_m_w4 <= lfsr_data_m_w3;
      end
   end

   always @ (posedge clk90) begin  
      if (rst90_r == 1'b1)
        lfsr_ena_r <= 1'b0;
      else if (u_data_val == 1'b1)
        lfsr_ena_r <= 1'b1;
      else
        lfsr_ena_r <= 1'b0;
   end
   
   always @ (posedge clk90) begin  
      if (rst90_r == 1'b1)
        lfsr_ena_w <= 1'b0;
      else if ((r_w == 1'b0) && (u_ack == 1'b1))
        lfsr_ena_w <= 1'b1;
      else
        lfsr_ena_w <= 1'b0;
   end

   always@(posedge clk90) begin
      if(rst90_r == 1'b1)
        u_dat_flag <= 1'b0;
      else
        u_dat_flag  <= cmd_ack;
   end

   assign u_dat_fl = { cmd_ack && !u_dat_flag && r_w};
   assign lfsr_rst_r1 = u_dat_fl ;

   always@(posedge clk90) begin
      if(rst90_r == 1'b1)
        lfsr_rst_r <= 1'b0;
      else
        lfsr_rst_r  <= lfsr_rst_r1;
   end

   ddr2_32Mx32_addr_gen_0  INST1
      (
       .clk        (clk),
       .rst180     (fpga_rst180),
       .addr_rst   (addr_rst),
       .addr_inc   (addr_inc),
       .addr_out   (addr_out),
       .burst_done (burst_done),
       .r_w        (r_w),
       .cnt_roll   (cnt_roll)
        );

   ddr2_32Mx32_cmd_fsm_0  INST_2
     (
      .clk          (clk),
      .clk90        (clk90),
      .auto_ref_req (auto_ref_req),
      .cmd_ack      (cmd_ack),
      .cnt_roll     (cnt_roll),
      .r_w          (r_w),
      .refresh_done (ar_done),
      .rst90        (fpga_rst90),
      .rst180       (fpga_rst180),
      .init_val     (init_done),
      .addr_inc     (addr_inc),
      .addr_rst     (addr_rst),
      .u_cmd        (u_cmd),
      .lfsr_rst     (lfsr_rst_w)
      );

   ddr2_32Mx32_cmp_data_0   INST3
     (
      .clk90            (clk90),
      .data_valid       (data_valid),
      .lfsr_data        (lfsr_data_r),
      .read_data        (u_data_o),
      .rst90            (fpga_rst90),
      .led_error_output (led_error_output),
      .data_valid_out   (data_valid_out)
       );

   ddr2_32Mx32_lfsr32_0     INST5
     (
      .clk90       (clk90),
      .rst90       (fpga_rst90),
      .lfsr_rst    (lfsr_rst_w),
      .lfsr_ena    (lfsr_ena_w),
      .lfsr_data_m (lfsr_data_m_w0),
      .lfsr_out    (lfsr_data_w0)
       );

   ddr2_32Mx32_lfsr32_0     INST7
     (
      .clk90       (clk90),
      .rst90       (fpga_rst90),
      .lfsr_rst    (lfsr_rst_r),
      .lfsr_ena    (lfsr_ena_r),
      .lfsr_data_m (lfsr_data_m_r),
      .lfsr_out    (lfsr_data_r)
      );
   
endmodule