ddr2_32mx32_lfsr32_0.v

Xilinx DDR2存储器接口调试代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_lfsr32_0.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:18 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module generate the user input data for hardware test.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
`include "../rtl/ddr2_32Mx32_parameters_0.v"

module    ddr2_32Mx32_lfsr32_0
  (
   input                               clk90,
   input                               rst90,
   input                               lfsr_rst,
   input                               lfsr_ena,
   output [((`DATA_WIDTH*2)-1):0]      lfsr_out,
   output [((`DATA_MASK_WIDTH*2)-1):0] lfsr_data_m
   );


   reg [7:0] lfsr_r;
   reg [7:0] lfsr_f;
   reg       rst90_r;


   assign lfsr_data_m = `DATA_MASK_WIDTH*2'd0;

   assign lfsr_out    = {  lfsr_r,  lfsr_r,  lfsr_r,  lfsr_r,    lfsr_f,    lfsr_f,    lfsr_f,    lfsr_f};

   always @( posedge clk90 )
           rst90_r <= rst90;

   always @ (posedge clk90) begin
      if (rst90_r == 1'b1) begin
         lfsr_r <= 'b0;
         lfsr_f <= 'd1;
      end
      else begin
         if (lfsr_rst == 1'b1) begin
            lfsr_r <= 'b0;
            lfsr_f <= 'd1;
         end
         else if (lfsr_ena == 1'b1) begin
            lfsr_r <= lfsr_r + 2;
            lfsr_f <= lfsr_f + 2;
         end
         else begin
            lfsr_f <= lfsr_f ;
            lfsr_r <= lfsr_r;
         end
      end
   end

endmodule