ddr2_32mx32_addr_gen_0.v

Xilinx DDR2存储器接口调试代码

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_addr_gen_0.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:17 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module generates address and burst done signals to the 
//		  controller.
////////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
`include "../rtl/ddr2_32Mx32_parameters_0.v"

module ddr2_32Mx32_addr_gen_0
  (
   input                          clk,
   input                          rst180,
   input                          addr_rst,
   input                          addr_inc,
   input                          r_w,
   output [((`ROW_ADDRESS +
             `COL_AP_WIDTH +
	     `BANK_ADDRESS)-1):0] addr_out,
   output                         burst_done,
   output                         cnt_roll
   );


   reg [7:0] 		    column_counter;
   reg [2:0] 		    burst_cnt;
   reg [1:0] 		    cnt;
   reg [1:0] 		    cnt1;
   reg [`BANK_ADDRESS-1:0]  ba_count;
   reg [(`ROW_ADDRESS-1):0] row_address1;
   reg                      burst_done_r1;
   reg                      burst_done_r2;
   reg                      burst_done_r3;
   reg                      burst_done_r4;
   reg                      burst_done_r5;
   reg                      rst180_r;
   wire [2:0] 		    burst_length;
   wire [3:0] 		    col_incr;
   wire [1:0] 		    col_val;
   wire [`ROW_ADDRESS - 1:0] lmr;
 
              
   assign lmr          = `LOAD_MODE_REGISTER;

   assign addr_out     = {row_address1, {`COL_AP_WIDTH -8{1'b0}},
                         column_counter, ba_count};

   assign burst_length = lmr[2:0];

   assign burst_done   = (burst_length == 3'b011 ? burst_done_r4 : burst_done_r2);

   assign cnt_roll     = (burst_length == 3'b011 ? burst_done_r3 : burst_done_r1);

   assign col_incr     = ((burst_length == 3'b011) ? 4'b1000 : 
			 ((burst_length == 3'b010) ? 4'b0100 : 4'b0000));

   assign col_val      = ((burst_length == 3'b011) ? 2'b11 : 
			 ((burst_length == 3'b010) ? 2'b01 : 2'b00));

   always @ (negedge clk) begin
      rst180_r <= rst180;
   end

   always @ (negedge clk) begin
      if(rst180_r == 1'b1 || row_address1[5] == 1'b1)
	row_address1 <=  {{(`ROW_ADDRESS-3){1'b0}}, 2'b10};
      else if( r_w == 1'b1 && burst_done_r4 == 1'b0 &&
	       burst_done_r5 == 1'b1)
	row_address1 <=  row_address1 + 8'b10;
      else
	row_address1 <=  row_address1;
   end

   always @ (negedge clk) begin
      if(rst180_r == 1'b1)
	ba_count <=  2'b00;
      else if( r_w == 1'b1 && burst_done_r4 == 1'b0 &&
	       burst_done_r5 == 1'b1)
	ba_count <=  ba_count + 1'b1;
      else
	ba_count <=  ba_count;
   end

   always @ (negedge clk) begin
      if (rst180_r == 1'b1 || addr_rst == 1'b1) 
        cnt <= 2'b0;
      else if (addr_inc == 1'b1 && cnt1 == 2'b01)  
	if (cnt == col_val)  
	  cnt <= 2'b0;
	else
	  cnt <= cnt + 1'b1;
   end

   always @ (negedge clk) begin
      if (rst180_r == 1'b1 || addr_rst == 1'b1) 
        burst_cnt <= 2'b0;
      else if (addr_inc == 1'b1 && cnt == 2'b00)  
	burst_cnt <= burst_cnt + 1'b1;
      else
	burst_cnt <= burst_cnt;
   end

   always @ (negedge clk) begin
      if (rst180_r == 1'b1 || addr_rst == 1'b1) begin
         column_counter <= 8'b0;
	 cnt1           <= 2'b0;
      end
      else if(addr_inc == 1'b1)
        if(cnt1 == 2'b0)
          cnt1 <= cnt1 + 1'b1;
	else if(cnt1 == 2'b01 && cnt == 2'b00 && burst_cnt < 3'b101)
          column_counter <= column_counter + col_incr;
	else
          column_counter <= column_counter;
      else if(!burst_done_r4  && burst_done_r5) 
        column_counter <= 8'd0;
   end

   always @ (negedge clk) begin
      burst_done_r1 <= (!rst180_r && (burst_cnt[2:0] == 3'b101));
   end

   always @ (negedge clk)begin
      burst_done_r2 <= burst_done_r1;
      burst_done_r3 <= burst_done_r2;
      burst_done_r4 <= burst_done_r3;
      burst_done_r5 <= burst_done_r4;
   end
   
endmodule