ddr2_32mx32_cmp_data_0.v

Xilinx DDR2存储器接口调试代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_cmp_data_0.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:17 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module compare the read data with written data and 
//		  generates the error signal in case of data mismatch.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
`include "../rtl/ddr2_32Mx32_parameters_0.v"

module  ddr2_32Mx32_cmp_data_0
  (
   input                         clk90,
   input                         rst90,
   input                         data_valid,
   input [((`DATA_WIDTH*2)-1):0] lfsr_data,
   input [((`DATA_WIDTH*2)-1):0] read_data,
   output                        led_error_output,
   output                        data_valid_out
   );

   reg 			       led_state;
   reg 			       valid;
   reg [((`DATA_WIDTH/8)-1):0] byte_err_fall/* synthesis syn_preserve=1 */;
   reg [((`DATA_WIDTH/8)-1):0] byte_err_rise/* synthesis syn_preserve=1 */;
   reg 			       val_reg;
   reg [((`DATA_WIDTH*2)-1):0] read_data_reg;
   reg 			       rst90_r;
   wire 		       error/* synthesis syn_keep=1 */;


   assign led_error_output = led_state;       

   assign data_valid_out   = valid;

   assign error            = ((|(byte_err_fall[((`DATA_WIDTH/8)-1):0])) || 
                              (|(byte_err_rise[((`DATA_WIDTH/8)-1):0]))) 
			       && val_reg;




   genvar err_i;
   generate for(err_i = 0; err_i < `DATA_WIDTH/8;  err_i = err_i + 1) begin: gen_byte_err
      always @ (posedge clk90) begin
         byte_err_fall[err_i]  <= (read_data_reg[err_i*8+:8] != lfsr_data[err_i*8+:8]);
         byte_err_rise[err_i] <= (read_data_reg[err_i*16+:16] != lfsr_data[err_i*16+:16]);
      end
    end
   endgenerate


  always @( posedge clk90 )
    rst90_r <= rst90;

  always @ (posedge clk90)
    read_data_reg <= read_data;

   always @ (posedge clk90) begin
      if (rst90_r == 1'b1) 
        valid   <= 1'b0;
      else 
        valid   <= data_valid;
   end

   always @ (posedge clk90) begin
      if (rst90_r == 1'b1)
        val_reg <= 1'b0;
      else
        val_reg <= valid;
   end


   always @ (posedge clk90) 
     led_state <= ( !rst90_r  && ( error || led_state));

   //synthesis translate_off 
   always @ (posedge clk90) begin
      if (rst90_r == 1'b0)
        if (error == 1'b1)
	  $display ("DATA ERROR at time %t byte_err_fall= %b ,byte_err_rise= %b" , 
		    $time,byte_err_fall,byte_err_rise);
   end 
   //synthesis translate_on

endmodule