ddr2_32mx32_cmd_fsm_0.v

Xilinx DDR2存储器接口调试代码

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_cmd_fsm_0.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:17 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module generate the commands to the controller.
////////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
`include "../rtl/ddr2_32Mx32_parameters_0.v"

module ddr2_32Mx32_cmd_fsm_0
  (
   input            clk,
   input            clk90,
   input            rst180,
   input            rst90,
   input            cmd_ack,
   input            cnt_roll,
   input            refresh_done,
   input            init_val,
   input            auto_ref_req,
   output reg       r_w,
   output reg       addr_inc,
   output           addr_rst,
   output reg [2:0] u_cmd,
   output           lfsr_rst
   );

   localparam RST_ST	    = 3'b000;
   localparam INIT_START_ST = 3'b001;
   localparam INIT_ST       = 3'b010;
   localparam WR_ST         = 3'b011;
   localparam DLY_ST        = 3'b100;
   localparam RD_ST         = 3'b101;

   reg [2:0]  current_state;
   reg [2:0]  next_state;
   reg [5:0]  init_dly;
   reg        lfsr_rst_180;
   reg        lfsr_rst_90;
   reg        init_done;
   reg        rst_flag;
   reg        temp;
   reg        rst90_r;
   reg        rst180_r;
   wire [5:0] init_dly_p;
   wire [2:0] u_cmd_p;
   wire       addr_inc_p;
   wire       lfsr_rst_p;
   wire       next_cmd;


   assign lfsr_rst    = lfsr_rst_90;

   assign u_cmd_p     = (current_state == RD_ST ) ? 3'b110 :
			(current_state == WR_ST)? 3'b100 :
			(current_state == INIT_START_ST)? 3'b010 :
                        3'b000;

   assign addr_inc_p  = ((cmd_ack == 1'b1) && (current_state == WR_ST ||
                                              current_state == RD_ST));

   assign addr_rst    = rst_flag ;

   assign lfsr_rst_p  = (r_w == 1'b1) ? 1'b1 : 1'b0 ;

   assign init_dly_p  = ((current_state == INIT_START_ST) ? 6'b111111 :
			((init_dly != 6'b000000) ? (init_dly - 1'b1) :
			 6'b000000));

   assign next_cmd    = ((cmd_ack == 1'b0) && (current_state == DLY_ST));


   always @ (negedge clk) begin
      rst_flag	<= ( !rst180_r && !cmd_ack && !temp);
      temp      <= ( !rst180_r && !cmd_ack);
   end

   always @( posedge clk90 )
     rst90_r <= rst90;

   always @( negedge clk )
     rst180_r <= rst180;

   always @ (negedge clk) begin
      if (rst180_r == 1'b1)
        lfsr_rst_180  <= 1'b0;
      else
        lfsr_rst_180  <= lfsr_rst_p;
   end

   always @ (posedge clk90) begin
      if (rst90_r == 1'b1)
        lfsr_rst_90  <= 1'b0;
      else 
        lfsr_rst_90  <= lfsr_rst_180;
   end

   always @ (negedge clk) begin
      if (rst180_r == 1'b1) 
        u_cmd <= 3'b000;
      else 
        u_cmd <= u_cmd_p;
   end


   always @ (negedge clk) begin
      if (rst180_r == 1'b1) begin
         addr_inc  <= 1'b0;
         init_dly  <= 6'b000000;
      end
      else begin
         addr_inc  <= addr_inc_p;
         init_dly  <= init_dly_p;
      end
   end

   always @ (negedge clk) begin
      if (rst180_r == 1'b1)
        init_done <= 1'b0;
      else
        init_done <= init_val;
   end

   always @(negedge clk) begin
      if(rst180_r == 1'b1)
        r_w <= 1'b0;
      else
        if(cmd_ack == 1'b0 && current_state == RD_ST )
          r_w <= 1'b1;
        else if(cmd_ack == 1'b0 && current_state == WR_ST )
          r_w <= 1'b0;
        else
          r_w  <= r_w;
   end


   always @ ( * ) begin
      if (rst180_r == 1'b1)
        next_state = RST_ST;
      else begin
         case (current_state)
           RST_ST :
             next_state = INIT_START_ST;
           
           INIT_START_ST : 
             next_state = INIT_ST;
                      
           INIT_ST : begin
              if (init_done == 1'b1)
                next_state = WR_ST;
              else
                next_state = INIT_ST;
           end

           WR_ST :  begin
              if (cnt_roll == 1'b0)
                next_state = WR_ST;
              else
                next_state = DLY_ST;
           end
	      
           DLY_ST : begin
              if(next_cmd == 1'b1 && r_w == 1'b0)
                next_state = RD_ST;
              else if(next_cmd == 1'b1 && r_w == 1'b1)
                next_state = WR_ST;
              else
                next_state = DLY_ST;
           end
	   
           RD_ST : begin
              if (cnt_roll == 1'b0)
                next_state = RD_ST;
              else
                next_state = DLY_ST;
           end
	   
           default :
             next_state = RST_ST;
         endcase
      end
   end

   always @ (negedge clk) begin
      if (rst180_r == 1'b1) 
        current_state    <= RST_ST;
      else
        current_state    <= next_state;
   end
   
endmodule